FPGA Manager Architecture - 2021.2 English

Zynq UltraScale+ MPSoC Software Developer Guide

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2021.2 English

The following figure shows the architecture of the FPGA Manager.

Figure 1. FPGA Manager Architecture Block Diagram

Execution Flow

FPGA manager provides an abstraction for the user to load bitstream using Linux. The xilfpga library initializes the PCAP, CSUDMA and other hardware. For more details about xilfpga, see the XilFPGA section in the OS and Libraries Document Collection (UG643).

To load a bitstream, the FPGA manager allocates the required memory and invokes the EEMI API using the FPGA LOAD API ID. This request is a blocking call. The FPGA Manger waits for response from the TF-A and response is provided to the fpga core layer which passes it to the application. This is described in the following figure:

Figure 2. FPGA Manager Flow