A53 Memory Management Unit - 2021.2 English

Zynq UltraScale+ MPSoC Software Developer Guide

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2021.2 English

The memory management unit (MMU) controls table-walk hardware that accesses translation tables in main memory. The MMU translates virtual addresses to physical addresses and provides configurable 1-stage or 2-stage address translation. The MMU provides fine-grained memory system control through a set of virtual-to-physical address mappings and memory attributes held in page tables. These are loaded into the translation lookaside buffer (TLB) when a location is accessed.

To understand more about MMU features and functionality, see this link to the “Memory Management Unit” section of the Zynq UltraScale+ Device Technical Reference Manual (UG1085).