Platform Management in PS - 2021.2 English

Zynq UltraScale+ MPSoC Software Developer Guide

Document ID
Release Date
2021.2 English

To increase the scalability in the platform management unit (PMU), the Zynq UltraScale+ MPSoC supports multiple power domains such as:

  • Full Power Domain
  • Low Power Domain
  • Battery Power Domain
  • PL Power Domain

For details on the PMU and the optional PMU firmware (PMU firmware) functionality, see the Zynq UltraScale+ Device Technical Reference Manual (UG1085).

For more information on dynamically changing the PS clocks, see Clock and Frequency Management.

The PS block offers high levels of functionality and performance. At the same time, there is a strong need to optimize the power consumption of this block with respect to the functionality and performance that is necessary at each stage of the operation.

The Zynq UltraScale+ MPSoC has multiple power rails. Each rail can be turned off independently, or can use a different voltage. Many of the blocks on a specific power rail implement power-gating, which allows blocks to be gated off independently.

Examples of these power-gated domains are the: Arm® Cortex®-A53 and the Cortex®-R5F processors, GPU pixel processors (PP), large RAMs, and individual USBs.

The following figure shows a block diagram of the platform management at the PS level.

Figure 1. Platform Management at the PS Level

From the power perspective, Zynq UltraScale+ MPSoCs offers the following modes of operation at the PS level:

  • Full-power operation mode
  • Low-power operation mode
  • Deep-sleep mode
  • Shutdown mode
  • Battery-power mode

The following sections describe these modes.