Known Issues and Limitations - 2021.1 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
Release Date
2021.1 English

This is a list of issues that might be encountered when using Dynamic Function eXchange (DFX) in the current Vivado® Design Suite release. If you encounter any of these issues, or discover any others, contact Xilinx® Support and send an example design that shows the issue. These test cases are very helpful to improve the overall solution.

Report to Xilinx all cases of fatal or internal errors, incomplete routing (partial antennas), or other rule violations that prevent place and route, pr_verify, and write_bitstream from succeeding. Including a design showing the failure is critical for proper analysis and implementation of fixes.

  • If the initial configuration of a 7 series SSI device (7V2000T, 7VX1140T) is done through an SPI interface, partial bitstreams cannot be delivered to the master (or any) ICAP; they must be delivered to an external port, such as JTAG. If the initial configuration is done through any other configuration port, the master ICAP can be used as the delivery port for partial bitstreams. Contact Xilinx Support for a workaround.
  • Do not drive multiple outputs of a single RM with the same source. Each output of an RM must have a unique driver.
  • When using Virtex UltraScale+ VU29P devices, connections between the IBUFDS_GTM and GTM_DUAL sites might be unroutable if the placer does not place them on the same SLR and the same side of the device. You might encounter route_design Route 35-7 in this case. If this occurs, you must LOC both the IBUFDS_GTM and GTM_DUAL instances to appropriate locations in the same SLR on the same side of the device.
  • Engineering Silicon (ES) for UltraScale™ or UltraScale+™ devices does not officially support Dynamic Function eXchange. To investigate the capabilities of DFX on ES devices, contact Xilinx Support for advice.