Configuration Frames - 2021.1 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
Release Date
2021.1 English

All user-programmable features inside Xilinx FPGA and SoC devices are controlled by volatile memory cells that must be configured at power-up. These memory cells are collectively known as configuration memory. They define the LUT equations, signal routing, IOB voltage standards, and all other aspects of the design.

Xilinx FPGA and SoC architectures have configuration memory arranged in frames that are tiled about the device. These frames are the smallest addressable segments of the device configuration memory space, and all operations must therefore act upon whole configuration frames.

Reconfigurable Frames are built upon these configuration frames, and these are the minimum building blocks for performing dynamic reconfiguration.

  • Base Regions in 7 series FPGAs are:
    50 high by 1 wide
    10 high by 1 wide
    Block RAM
    10 high by 1 wide
  • Base Regions in UltraScale and UltraScale+ FPGAs are:
    60 high by 1 wide
    24 high by 1 wide
    Block RAM
    12 high by 1 wide
    I/O and Clocking
    52 I/O (one bank), plus related XiPhy, MMCM, and PLL resources
    Gigabit Transceivers
    Four high (one quad, plus related clocking resources)