Similar to UltraScale+ architecture, the
expansion of routing area also happens in Versal for logical signals. The
routing footprint of a reconfigurable Pblock can be understood by sourcing the script
called <pblock_name>_routing_tiles.tcl in hd_visual folder of implementation directory. For clock
routing, the necessary clock routing tiles (for example, CLK_VNOC) of RP Pblock are
automatically pulled into the routing footprint.
Warning: The Expanded Routing feature should not be disabled for Versal devices to ensure the highest possibility of routing
success.