Black Boxes - 2021.1 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

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2021.1 English

You can implement an RP as a pseudo black box, referred to in Vivado as a graybox. To do this, the RP must be a black box in the static design (either from bottom-up synthesis results or from running update_design -black_box). Then the black box can have LUT1 buffers placed on all inputs and outputs using the command update_design -buffer_ports on the black box RP cell:

update_design -cell <rp_cellName> -buffer_ports

Now you can run this design through implementation to place and route the LUT1 buffers (and static logic, if not already placed and routed).

All the inserted LUT1 output buffers are tied to a logic 0 (ground). If it is necessary to drive a logic 1 (VCC) from the RP outputs, this can be controlled using an RP pin property called HD.PARTPIN_TIEOFF. This property can be set at any time (all the way up to pre-write_bitstream), and it controls the LUT equation of the LUT1 buffer connected to the specified port. The default value is '0', which configures the LUT as a route-thru (output is 0). Setting this property to '1' configures the LUT as an inverter (output is 1). You might have to change the output value in some design situations.

set_property HD.PARTPIN_TIEOFF 1 [get_pins <RP_cellName>/<output_pinName>]

The graybox has no user logic (just the tool-inserted LUT1 buffers). The graybox bitstream contains information for these LUTs, as well as any static logic/routes that use resources inside the RP frames. Static routes that pass through the region, including interface nets up to the partition pin nodes, exist within this region. Programming information for these signals is included in the black box programming bitstream.

Use of grayboxes is an effective way to reduce the size of a full configuration BIT file, and therefore reduce the initial configuration time. The compression feature might also be enabled to reduce the size of BIT files. This option looks for repeated configuration frame structures to reduce the amount of configuration data that must be stored in the BIT file. The compression results in reduced configuration and reconfiguration time. When the compression option is applied to a routed DFX design, all of the BIT files (full and partial) are created as compressed BIT files. To enable compression, set this property prior to running write_bitstream:

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]