Summary of BIT Files for UltraScale Devices - 2021.1 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2022-02-25
Version
2021.1 English

This section applies specifically to UltraScale devices and does not apply to 7 series, UltraScale+, Zynq, or Zynq MPSoC devices. With the finer granularity of global signals (that is, GSR) and the ability to reconfigure new element types, a new configuration process is necessary. Prior to loading in a partial bitstream for a new RM, the existing RM must be cleared. This clearing bitstream prepares the device for delivery of any subsequent partial bitstream for that RP by establishing the global signal mask for the region to be reconfigured. Although the existing module technically is not removed, it is easiest to think of it this way.

When running write_bitstream on a design configuration with RPs, a clearing BIT file per RP is created. For example, take a design in which two RPs (RP1 and RP2), with two RMs each, A1 and B1 into RP1, and A2 and B2 into RP2, have been implemented. Two configurations (configA and configB) have been run through place and route, and pr_verify has passed. When bitstreams are generated, each configuration produces five bitstreams. For configA, these could be named:

configA.bit
This is the full design bitstream that is used to configure the device from power-up. This contains the static design plus functions A1 and A2.
configA_RP1_A1_partial.bit
This is the partial BIT file for function A1. This is loaded after another RM has been cleared from this RP.
configA_RP1_A1_partial_clear.bit
This is the clearing BIT file for function A1. Before loading in any other partial BIT file into RP1 after function A1, this file must be loaded.
configA_RP2_A2_partial.bit
This is the partial BIT file for function A2. This is loaded after another RM has been cleared from this RP.
configA_RP2_A2_partial_clear.bit
This is the clearing BIT file for function A2. Before loading in any other partial BIT file into RP2 after function A2, this file must be loaded.

Likewise, configB produces five similar bitstreams:

configB.bit
This is the full design bitstream that is used to configure the device from power-up. This contains the static design plus functions B1 and B2.
configB_RP1_B1_partial.bit
This is the partial BIT file for function B1. This is loaded after another RM has been cleared from this RP.
configB_RP1_B1_partial_clear.bit
This is the clearing BIT file for function B1. Before loading in any other partial BIT file into RP1 after function B1, this file must be loaded.
configB_RP2_B2_partial.bit
This is the partial BIT file for function B2. This is loaded after another RM has been cleared from this RP.
configB_RP2_B2_partial_clear.bit
This is the clearing BIT file for function B2. Before loading in any other partial BIT file into RP2 after function B2, this file must be loaded.

The sequence for any reconfiguration is to first load a clearing BIT file for a current RM, immediately followed by a new RM. For example, to transition RP RP1 from function A1 to function B1, first load the BIT file configA_RP1_A1_partial_clear.bit, then load configB_RP1_B1_partial.bit. The first bitstream prepares the region by opening the mask, and the second bitstream loads the new function, initializes only that region, then closes the mask.

If a clearing bit file is not loaded, initialization routines (GSR) have no effect. If a clearing file for a different RP is loaded, then that RP is initialized instead of the one that has been just reconfigured. If the incorrect clearing file for the proper RP is used, the current RM or possibly even the static design could be disrupted until the following partial bit file has been loaded.