Functions - 2021.1 English

Vitis High-Level Synthesis User Guide (UG1399)

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2021.1 English

The top-level function becomes the top level of the RTL design after synthesis. Sub-functions are synthesized into blocks in the RTL design.

Important: The top-level function cannot be a static function.

After synthesis, each function in the design has its own synthesis report and HDL file (Verilog and VHDL).