pragma HLS protocol - 2021.1 English

Vitis High-Level Synthesis User Guide (UG1399)

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2021.1 English


This commands specifies a region of code, a protocol region, in which no clock operations will be inserted by Vitis HLS unless explicitly specified in the code. Vitis HLS will not insert any clocks between operations in the region, including those which read from or write to function arguments. The order of read and writes will therefore be strictly followed in the synthesized RTL.

A region of code can be created in the C/C++ code by enclosing the region in braces "{ }" and naming it. The following defines a region named io_section:
lines of code

A clock operation can be explicitly specified in C/C++ code using an ap_wait() statement, and may be specified in C++ code by using the wait() statement. The ap_wait and wait statements have no effect on the simulation of the design.


Place the pragma in the C source within the body of the function or protocol region.

#pragma HLS protocol [floating | fixed]


Lets code statements outside the protocol region overlap and execute in parallel with statements in the protocol region in the final RTL. The protocol region remains cycle accurate, but outside operations can occur at the same time. This is the default mode.
The fixed mode ensures that statements outside the protocol region do not execute in parallel with the protocol region.


This example defines a protocol region, io_section in function foo where the pragma defines that region as a floating protocol region as the default mode:

io_section: {
#pragma HLS protocol