In the S_AXILITE Example all
the function arguments are grouped into a single s_axilite
interface adapter specified by the bundle=BUS_A
option in the INTERFACE pragma.
The bundle
option simply lets you group
ports together into one interface.
s_axi_control
by the tool. So you should not
specify the bundle
option in that flow, or
you will probably encounter an error during synthesis. However, in the
Vivado IP flow you can specify
multiple bundles using the s_axilite
interface, and this will create a separate interface adapter for each bundle
you have defined. The following example shows
this:void example(char *a, char *b, char *c)
{
#pragma HLS INTERFACE mode=s_axilite port=a bundle=BUS_A
#pragma HLS INTERFACE mode=s_axilite port=b bundle=BUS_A
#pragma HLS INTERFACE mode=s_axilite port=c bundle=OUT
#pragma HLS INTERFACE mode=s_axilite port=return bundle=BUS_A
#pragma HLS INTERFACE mode=ap_vld port=b
*c += *a + *b;
}
After synthesis completes, the Synthesis Summary report
provides feedback regarding the number of s_axilite
adapters generated. The SW-to-HW Mapping section of the
report contains the HW info showing the control register offset and the
address range for each port.
However, there are some rules related to using bundles with
the s_axilite
interface.
- Default Bundle Names: This rule explicitly groups all
interface ports with no bundle name into the same AXI4-Lite interface port, uses the
tool default bundle name, and names the RTL port
s_axi_<default>
, typicallys_axi_control
.In this example all ports are mapped to the default bundle:void top(char *a, char *b, char *c) { #pragma HLS INTERFACE mode=s_axilite port=a #pragma HLS INTERFACE mode=s_axilite port=b #pragma HLS INTERFACE mode=s_axilite port=c *c += *a + *b; }
- User-Specified Bundle Names: This rule explicitly
groups all interface ports with the same
bundle
name into the same AXI4-Lite interface port, and names the RTL port the value specified bys_axi_<string>
.The following example results in interfaces nameds_axi_BUS_A
,s_axi_BUS_B
, ands_axi_OUT
:void example(char *a, char *b, char *c) { #pragma HLS INTERFACE mode=s_axilite port=a bundle=BUS_A #pragma HLS INTERFACE mode=s_axilite port=b bundle=BUS_B #pragma HLS INTERFACE mode=s_axilite port=c bundle=OUT #pragma HLS INTERFACE mode=s_axilite port=return bundle=OUT #pragma HLS INTERFACE mode=ap_vld port=b *c += *a + *b; }
- Partially Specified Bundle Names: If you specify
bundle
names for some arguments, but leave other arguments unassigned, then the tool will bundle the arguments as follows:- Group all ports into the specified bundles as indicated by the INTERFACE pragmas.
- Group any ports without bundle assignments into a default named bundle. The default name can either be the standard tool default, or an alternative default name if the tool default has already been specified by the user.
In the following example the user has specified
bundle=control
, which is the tool default name. In this case, port c will be assigned tos_axi_control
as specified by the user, and the remaining ports will be bundled unders_axi_control_r
, which is an alternative default name used by the tool.void top(char *a, char *b, char *c) { #pragma HLS INTERFACE mode=s_axilite port=a #pragma HLS INTERFACE mode=s_axilite port=b #pragma HLS INTERFACE mode=s_axilite port=c bundle=control }