Explicitly limiting the number of operators to reduce area may be required in some cases: the default operation of Vitis HLS is to first maximize performance. Limiting the number of operators in a design is a useful technique to reduce the area of the design: it helps reduce area by forcing the sharing of operations. However, this might cause a decline in performance.
The ALLOCATION directive allows you to limit how many operators are used in a
design. For example, if a design called foo
has 317
multiplications but the FPGA only has 256 multiplier resources (DSP macrocells). The
ALLOCATION pragma shown below directs Vitis HLS to create a design with
a maximum of 256 multiplication (mul
) operators:
dout_t array_arith (dio_t d[317]) {
static int acc;
int i;
#pragma HLS ALLOCATION instances=mul limit=256 operation
for (i=0;i<317;i++) {
#pragma HLS UNROLL
acc += acc * d[i];
}
rerun acc;
}
You can use the type
option to specify if the
ALLOCATION directives limits operations, implementations, or functions. The following table
lists all the operations that can be controlled using the ALLOCATION directive.
Operator | Description |
---|---|
add | Integer Addition |
ashr | Arithmetic Shift-Right |
dadd | Double-precision floating-point addition |
dcmp | Double-precision floating-point comparison |
ddiv | Double-precision floating-point division |
dmul | Double-precision floating-point multiplication |
drecip | Double-precision floating-point reciprocal |
drem | Double-precision floating-point remainder |
drsqrt | Double-precision floating-point reciprocal square root |
dsub | Double-precision floating-point subtraction |
dsqrt | Double-precision floating-point square root |
fadd | Single-precision floating-point addition |
fcmp | Single-precision floating-point comparison |
fdiv | Single-precision floating-point division |
fmul | Single-precision floating-point multiplication |
frecip | Single-precision floating-point reciprocal |
frem | Single-precision floating point remainder |
frsqrt | Single-precision floating-point reciprocal square root |
fsub | Single-precision floating-point subtraction |
fsqrt | Single-precision floating-point square root |
icmp | Integer Compare |
lshr | Logical Shift-Right |
mul | Multiplication |
sdiv | Signed Divider |
shl | Shift-Left |
srem | Signed Remainder |
sub | Subtraction |
udiv | Unsigned Division |
urem | Unsigned Remainder |