Description
Specifies a minimum or maximum latency value, or both, for the completion of functions, loops, and regions.
- Latency
- Number of clock cycles required to produce an output.
- Function latency
- Number of clock cycles required for the function to compute all output values, and return.
- Loop latency
- Number of cycles to execute all iterations of the loop.
Vitis HLS always tries to minimize latency in the design. When the LATENCY pragma is specified, the tool behavior is as follows:
- Latency is greater than the minimum, or less than the maximum: The constraint is satisfied. No further optimizations are performed.
- Latency is less than the minimum: If the HLS tool can achieve less than the minimum specified latency, it extends the latency to the specified value, potentially enabling increased sharing.
- Latency is greater than the maximum: If the HLS tool cannot schedule within the maximum limit, it increases effort to achieve the specified constraint. If it still fails to meet the maximum latency, it issues a warning, and produces a design with the smallest achievable latency in excess of the maximum.
Syntax
Place the pragma within the boundary of a function, loop, or region of code where the latency must be managed.
#pragma HLS latency min=<int> max=<int>Where:
-
min=<int> - Optionally specifies the minimum latency for the function, loop, or region of code.
-
max=<int> - Optionally specifies the maximum latency for the function, loop, or region of code.
Example 1
Function foo is specified to have a
minimum latency of 4 and a maximum latency of 8.
int foo(char x, char a, char b, char c) {
#pragma HLS latency min=4 max=8
char y;
y = x*a+b+c;
return y
}Example 2
In the following example, loop_1 is
specified to have a maximum latency of 12. Place the pragma in the loop body as shown.
void foo (num_samples, ...) {
int i;
...
loop_1: for(i=0;i< num_samples;i++) {
#pragma HLS latency max=12
...
result = a + b;
}
}Example 3
The following example creates a code region and groups signals that need to change in the same clock cycle by specifying zero latency.
// create a region { } with a latency = 0
{
#pragma HLS LATENCY max=0 min=0
*data = 0xFF;
*data_vld = 1;
}