Parameterized Macro: Single-bit Synchronizer
- MACRO_GROUP: XPM
- MACRO_SUBGROUP: XPM_CDC
Introduction
This macro synchronizes a one bit signal from the source clock domain to the destination clock domain.
For proper operation, the input data must be sampled two or more times by the destination clock. You can define the number of register stages used in the synchronizers. An optional input register may be used to register the input in the source clock domain prior to it being synchronized. You can also enable a simulation feature to generate messages to report any potential misuse of the macro.
Port Descriptions
Port | Direction | Width | Domain | Sense | Handling if Unused | Function |
---|---|---|---|---|---|---|
dest_clk | Input | 1 | NA | EDGE_RISING | Active | Clock signal for the destination clock domain. |
dest_out | Output | 1 | dest_clk | NA | Active | src_in synchronized to the destination clock domain. This output is registered. |
src_clk | Input | 1 | NA | EDGE_RISING | 0 |
Input clock signal for src_in if SRC_INPUT_REG = 1. Unused when SRC_INPUT_REG = 0. |
src_in | Input | 1 | src_clk | NA | Active | Input signal to be synchronized to dest_clk domain. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
DEST_SYNC_FF | DECIMAL | 2 to 10 | 4 | Number of register stages used to synchronize signal in the destination clock domain. |
INIT_SYNC_FF | DECIMAL | 0, 1 | 0 |
0- Disable behavioral simulation initialization value(s) on synchronization registers. 1- Enable behavioral simulation initialization value(s) on synchronization registers. |
SIM_ASSERT_CHK | DECIMAL | 0, 1 | 0 |
0- Disable simulation message reporting. Messages related to potential misuse will not be reported. 1- Enable simulation message reporting. Messages related to potential misuse will be reported. |
SRC_INPUT_REG | DECIMAL | 1, 0 | 1 |
0- Do not register input (src_in) 1- Register input (src_in) once using src_clk |
VHDL Instantiation Template
Library xpm;
use xpm.vcomponents.all;
-- xpm_cdc_single: Single-bit Synchronizer
-- Xilinx Parameterized Macro, version 2021.1
xpm_cdc_single_inst : xpm_cdc_single
generic map (
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
SRC_INPUT_REG => 1 -- DECIMAL; 0=do not register input, 1=register input
)
port map (
dest_out => dest_out, -- 1-bit output: src_in synchronized to the destination clock domain. This output
-- is registered.
dest_clk => dest_clk, -- 1-bit input: Clock signal for the destination clock domain.
src_clk => src_clk, -- 1-bit input: optional; required when SRC_INPUT_REG = 1
src_in => src_in -- 1-bit input: Input signal to be synchronized to dest_clk domain.
);
-- End of xpm_cdc_single_inst instantiation
Verilog Instantiation Template
// xpm_cdc_single: Single-bit Synchronizer
// Xilinx Parameterized Macro, version 2021.1
xpm_cdc_single #(
.DEST_SYNC_FF(4), // DECIMAL; range: 2-10
.INIT_SYNC_FF(0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
.SRC_INPUT_REG(1) // DECIMAL; 0=do not register input, 1=register input
)
xpm_cdc_single_inst (
.dest_out(dest_out), // 1-bit output: src_in synchronized to the destination clock domain. This output is
// registered.
.dest_clk(dest_clk), // 1-bit input: Clock signal for the destination clock domain.
.src_clk(src_clk), // 1-bit input: optional; required when SRC_INPUT_REG = 1
.src_in(src_in) // 1-bit input: Input signal to be synchronized to dest_clk domain.
);
// End of xpm_cdc_single_inst instantiation