Primitive: Differential Bidirectional Buffer With Input Buffer Disable and On-die Input
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: BIDIR_BUFFER
Introduction
The IOBUFDS_INTERMDISABLE primitive is available in the HD I/O banks. It has an IBUFDISABLE port that can be used to disable the input buffer during periods when the buffer is not being used. The IOBUFDS_INTERMDISABLE primitive also has an INTERMDISABLE port that can be used to disable the optional on-die receiver termination feature.
The IOBUFDS_INTERMDISABLE primitive can disable the input buffer and force the O output to the internal logic to a logic-Low when the IBUFDISABLE signal is asserted High and the output buffer is 3-stated (T = High). The USE_IBUFDISABLE attribute must be set to TRUE and SIM_DEVICE to the appropriate value for this primitive to have the expected behavior that is specific to the architecture. If the I/O is using the on-die receiver termination feature, this primitive disables the termination legs whenever the INTERMDISABLE signal is asserted High and the output buffer is 3-stated. When the output buffer is 3-stated (T = High), the input buffer and any on-die receiver termination are controlled by IBUFDISABLE and INTERMDISABLE, respectively. When the output buffer is not 3-stated (T = Low), the input buffer and on-die receiver termination are disabled and the O output (to the internal logic) is forced to a logic-Low. These features can be combined to reduce power whenever the input is idle for a period of time.
I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DIFF_TERM, and IBUF_LOW_PWR, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
I | Input | 1 | Input of OBUF. Connect to the logic driving the output port. |
IBUFDISABLE | Input | 1 | Disables input path through the buffer and forces to a logic Low. This feature is generally used to reduce power at times when the I/O is idle for a period of time. |
INTERMDISABLE | Input | 1 | Control to enable/disable on-chip input termination. This is generally used to reduce power in long periods of an idle state. |
IO | Inout | 1 | Bidirectional diff_p port to be connected directly to top-level inout port. |
IOB | Inout | 1 | Bidirectional diff_n port to be connected directly to top-level inout port. |
O | Output | 1 | Output path of the buffer. |
T | Input | 1 | 3-state enable input signifying whether the buffer acts as an input or output. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
SIM_DEVICE | STRING | "VERSAL_AI_CORE", "VERSAL_AI_CORE_ES1", "VERSAL_AI_CORE_ES2" | "7SERIES" | Set the device version for simulation functionality. |
USE_IBUFDISABLE | STRING | "TRUE", "FALSE" | "TRUE" | Set this attribute to "TRUE" to enable the IBUFDISABLE pin. |
VHDL Instantiation Template
Library UNISIM;
use UNISIM.vcomponents.all;
-- IOBUFDS_INTERMDISABLE: Differential Bidirectional Buffer With Input Buffer Disable and On-die Input
-- Versal AI Core series
-- Xilinx HDL Language Template, version 2021.1
IOBUFDS_INTERMDISABLE_inst : IOBUFDS_INTERMDISABLE
generic map (
SIM_DEVICE => "VERSAL_AI_CORE", -- Set the device version for simulation functionality (VERSAL_AI_CORE,
-- VERSAL_AI_CORE_ES1)
USE_IBUFDISABLE => "TRUE" -- Enable/Disable the IBUFDISABLE pin (FALSE, TRUE)
)
port map (
O => O, -- 1-bit output: Buffer output
I => I, -- 1-bit input: Buffer input
IBUFDISABLE => IBUFDISABLE, -- 1-bit input: Buffer disable input, high=disable
INTERMDISABLE => INTERMDISABLE, -- 1-bit input: Input Termination Disable
IO => IO, -- 1-bit inout: Diff_p inout (connect directly to top-level port)
IOB => IOB, -- 1-bit inout: Diff_n inout (connect directly to top-level port)
T => T -- 1-bit input: 3-state enable input
);
-- End of IOBUFDS_INTERMDISABLE_inst instantiation
Verilog Instantiation Template
// IOBUFDS_INTERMDISABLE: Differential Bidirectional Buffer With Input Buffer Disable and On-die Input
// Versal AI Core series
// Xilinx HDL Language Template, version 2021.1
IOBUFDS_INTERMDISABLE #(
.SIM_DEVICE("VERSAL_AI_CORE"), // Set the device version for simulation functionality (VERSAL_AI_CORE,
// VERSAL_AI_CORE_ES1)
.USE_IBUFDISABLE("TRUE") // Enable/Disable the IBUFDISABLE pin (FALSE, TRUE)
)
IOBUFDS_INTERMDISABLE_inst (
.O(O), // 1-bit output: Buffer output
.I(I), // 1-bit input: Buffer input
.IBUFDISABLE(IBUFDISABLE), // 1-bit input: Buffer disable input, high=disable
.INTERMDISABLE(INTERMDISABLE), // 1-bit input: Input Termination Disable
.IO(IO), // 1-bit inout: Diff_p inout (connect directly to top-level port)
.IOB(IOB), // 1-bit inout: Diff_n inout (connect directly to top-level port)
.T(T) // 1-bit input: 3-state enable input
);
// End of IOBUFDS_INTERMDISABLE_inst instantiation
Related Information
- Versal ACAP SelectIO Resources Architecture Manual (AM010)