Primitive: 128-Deep by 1-Wide Random Access Memory (Select RAM)
- PRIMITIVE_GROUP: CLB
- PRIMITIVE_SUBGROUP: LUTRAM
Introduction
This design element is a 128-bit deep by 1-bit wide random access memory with synchronous write and asynchronous read capability. This RAM is implemented using the LUT resources of the device (also known as Select RAM), and does not consume any of the block RAM resources of the device. If a synchronous read capability is preferred, a register can be attached to the output and placed in the same CLB.
The RAM128X1S has an active-High write enable (WE) so that when that signal is High, and a rising edge occurs on the WCLK pin, a write is performed recording the value of the D input data pin into the memory array. The output O displays the contents of the memory cell addressed by A, regardless of the WE value. When a write is performed, the output is updated to the new value shortly after the write completes.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| O | Output | 1 | Read/Write port data output addressed by A |
| D | Input | 1 | Write data input addressed by A |
| A | Input | 7 | Read/Write port address bus |
| WE | Input | 1 | Write Enable |
| WCLK | Input | 1 | Write clock (reads are asynchronous) |
Design Entry Method
| Instantiation | Yes |
| Inference | Recommended |
| IP Catalog | No |
If instantiated, the following connections should be made to this component:
-
Tie the WCLK input to the desired clock source, the D input to the data source to be stored, and the O output to an FDCE D input or other appropriate data destination.
-
Connect the WE clock enable pin to the proper write enable source in the design.
-
Connect the 7-bit A bus to the source for the read/write.
You can use the INIT attribute to specify the initial contents of the RAM. If left unspecified, the initial contents default to all zeros.
Available Attributes
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
| INIT | HEX | Any 128-bit value | All zeros | Specifies the initial contents of the RAM. |
| IS_WCLK_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the WCLK pin. |
VHDL Instantiation Template
Library UNISIM;
use UNISIM.vcomponents.all;
-- RAM128X1S: 128-deep x 1 positive edge write, asynchronous read
-- single-port distributed RAM
-- Versal AI Core series
-- Xilinx HDL Language Template, version 2021.1
RAM128X1S_inst : RAM128X1S
generic map (
INIT => X"00000000000000000000000000000000", -- Initial contents of RAM
IS_WCLK_INVERTED => '0') -- Specifies active high/low WCLK
port map (
O => O, -- 1-bit data output
A0 => A0, -- Address[0] input bit
A1 => A1, -- Address[1] input bit
A2 => A2, -- Address[2] input bit
A3 => A3, -- Address[3] input bit
A4 => A4, -- Address[4] input bit
A5 => A5, -- Address[5] input bit
A6 => A6, -- Address[6] input bit
D => D, -- 1-bit data input
WCLK => WCLK, -- Write clock input
WE => WE -- RAM data input
);
-- End of RAM128X1S_inst instantiation
Verilog Instantiation Template
// RAM128X1S: 128 x 1 positive edge write, asynchronous read single-port
// distributed RAM (Mapped to two LUT6s)
// Versal AI Core series
// Xilinx HDL Language Template, version 2021.1
RAM128X1S #(
.INIT(128'h00000000000000000000000000000000), // Initial contents of RAM
.IS_WCLK_INVERTED(1'b0) // Specifies active high/low WCLK
) RAM128X1S_inst (
.O(O), // 1-bit data output
.A0(A0), // Address[0] input bit
.A1(A1), // Address[1] input bit
.A2(A2), // Address[2] input bit
.A3(A3), // Address[3] input bit
.A4(A4), // Address[4] input bit
.A5(A5), // Address[5] input bit
.A6(A6), // Address[6] input bit
.D(D), // 1-bit data input
.WCLK(WCLK), // Write clock input
.WE(WE) // Write enable input
);
// End of RAM128X1S_inst instantiation
Related Information
- Versal ACAP Configurable Logic Block Architecture Manual (AM005)