BUFG_PS - 2021.1 English

Versal Architecture AI Core Series Libraries Guide (UG1353)

Document ID
UG1353
Release Date
2021-06-16
Version
2021.1 English

Primitive: A high-fanout buffer for low-skew distribution of the PS Clock signals

  • PRIMITIVE_GROUP: CLOCK
  • PRIMITIVE_SUBGROUP: BUFFER

Introduction

A high-fanout buffer for low-skew distribution of the PS Clock signals.

Port Descriptions

Port Direction Width Function
I Input 1 Clock buffer input.
O Output 1 Clock buffer output.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- BUFG_PS: A high-fanout buffer for low-skew distribution of the PS Clock signals
--          Versal AI Core series
-- Xilinx HDL Language Template, version 2021.1

BUFG_PS_inst : BUFG_PS
port map (
   O => O, -- 1-bit output: Clock buffer output
   I => I  -- 1-bit input: Clock buffer input
);

-- End of BUFG_PS_inst instantiation

Verilog Instantiation Template


// BUFG_PS: A high-fanout buffer for low-skew distribution of the PS Clock signals
//          Versal AI Core series
// Xilinx HDL Language Template, version 2021.1

BUFG_PS BUFG_PS_inst (
   .O(O), // 1-bit output: Clock buffer output
   .I(I)  // 1-bit input: Clock buffer input
);

// End of BUFG_PS_inst instantiation

Related Information

  • Versal ACAP Clocking Resources Architecture Manual (AM003)