RAM64X1D - 2021.1 English

Versal Architecture AI Core Series Libraries Guide (UG1353)

Document ID
UG1353
Release Date
2021-06-16
Version
2021.1 English

Primitive: 64-Deep by 1-Wide Dual Port Static Synchronous RAM

  • PRIMITIVE_GROUP: CLB
  • PRIMITIVE_SUBGROUP: LUTRAM

Introduction

This design element is a 64-bit deep by 1-bit wide static dual port random access memory with synchronous write capability. The device has two separate address ports: the read address (DPRA5:DPRA0) and the write address (A5:A0). These two address ports are completely asynchronous. The read address controls the location of the data driven out of the output pin (DPO), and the write address controls the destination of a valid write transaction. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected.

When WE is High, any positive transition on WCLK loads the data on the data input (D) into the memory cell selected by the 6-bit (A0:A5) write address. For predictable performance, write address and data inputs must be stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.

The SPO output reflects the data in the memory cell addressed by A5:A0. The DPO output reflects the data in the memory cell addressed by DPRA5:DPRA0. The write process is not affected by the address on the read address port.

You can use the INIT attribute to specify the initial contents of the RAM. If left unspecified, the initial contents default to all zeros.

Logic Table

Inputs Outputs
WE (mode) WCLK D SPO DPO
0 (read) X X data_a data_d
1 (read) 0 X data_a data_d
1 (read) 1 X data_a data_d
1 (write) D D data_d
1 (read) X data_a data_d

data_a = memory cell addressed by bits A5:A0

data_d = memory cell addressed by bits DPRA5:DPRA0

Design Entry Method

Instantiation Yes
Inference Recommended
IP Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
INIT HEX Any 64-bit value All zeros Specifies the initial contents of the RAM.
IS_WCLK_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the WCLK pin.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- RAM64X1D: 64 x 1 positive edge write, asynchronous read
--           dual-port distributed RAM
--           Versal AI Core series
-- Xilinx HDL Language Template, version 2021.1

RAM64X1D_inst : RAM64X1D
generic map (
   INIT => X"0000000000000000", -- Initial contents of RAM
   IS_WCLK_INVERTED => '0') -- Specifies active high/low WCLK
port map (
   DPO => DPO,     -- Read-only 1-bit data output
   SPO => SPO,     -- R/W 1-bit data output
   A0 => A0,       -- R/W address[0] input bit
   A1 => A1,       -- R/W address[1] input bit
   A2 => A2,       -- R/W address[2] input bit
   A3 => A3,       -- R/W address[3] input bit
   A4 => A4,       -- R/W address[4] input bit
   A5 => A5,       -- R/W address[5] input bit
   D => D,         -- Write 1-bit data input
   DPRA0 => DPRA0, -- Read-only address[0] input bit
   DPRA1 => DPRA1, -- Read-only address[1] input bit
   DPRA2 => DPRA2, -- Read-only address[2] input bit
   DPRA3 => DPRA3, -- Read-only address[3] input bit
   DPRA4 => DPRA4, -- Read-only address[4] input bit
   DPRA5 => DPRA5, -- Read-only address[5] input bit
   WCLK => WCLK,   -- Write clock input
   WE => WE        -- Write enable input
);

-- End of RAM64X1D_inst instantiation

Verilog Instantiation Template


// RAM64X1D: 64 x 1 positive edge write, asynchronous read dual-port
//           distributed RAM (Mapped to two LUT6s)
//           Versal AI Core series
// Xilinx HDL Language Template, version 2021.1

RAM64X1D #(
   .INIT(64'h0000000000000000), // Initial contents of RAM
   .IS_WCLK_INVERTED(1'b0)      // Specifies active high/low WCLK
) RAM64X1D_inst (
   .DPO(DPO),     // Read-only 1-bit data output
   .SPO(SPO),     // Rw/ 1-bit data output
   .A0(A0),       // Rw/ address[0] input bit
   .A1(A1),       // Rw/ address[1] input bit
   .A2(A2),       // Rw/ address[2] input bit
   .A3(A3),       // Rw/ address[3] input bit
   .A4(A4),       // Rw/ address[4] input bit
   .A5(A5),       // Rw/ address[5] input bit
   .D(D),         // Write 1-bit data input
   .DPRA0(DPRA0), // Read-only address[0] input bit
   .DPRA1(DPRA1), // Read-only address[1] input bit
   .DPRA2(DPRA2), // Read-only address[2] input bit
   .DPRA3(DPRA3), // Read-only address[3] input bit
   .DPRA4(DPRA4), // Read-only address[4] input bit
   .DPRA5(DPRA5), // Read-only address[5] input bit
   .WCLK(WCLK),   // Write clock input
   .WE(WE)        // Write enable input
);

// End of RAM64X1D_inst instantiation

Related Information

  • Versal ACAP Configurable Logic Block Architecture Manual (AM005)