Primitive: Differential 3-state Output Buffer
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: OUTPUT_BUFFER
Introduction
The OBUFTDS is a differential 3-state output buffer primitive.
I/O attributes that do not impact the logic function of the component, such as IOSTANDARD and SLEW, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).
Logic Table
Inputs | Outputs | ||
---|---|---|---|
I | T | O | OB |
X | 1 | Z | Z |
0 | 0 | 0 | 1 |
1 | 0 | 1 | 0 |
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
I | Input | 1 | Buffer input. |
O | Output | 1 | Diff_p output. Connect directly to a top-level port in the design. |
OB | Output | 1 | Diff_n output. Connect directly to a top-level port in the design. |
T | Input | 1 | 3-state enable input. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | No |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- OBUFTDS: Differential 3-state Output Buffer
-- Versal AI Core series
-- Xilinx HDL Language Template, version 2021.1
OBUFTDS_inst : OBUFTDS
port map (
O => O, -- 1-bit output: Diff_p output (connect directly to top-level port)
OB => OB, -- 1-bit output: Diff_n output (connect directly to top-level port)
I => I, -- 1-bit input: Buffer input
T => T -- 1-bit input: 3-state enable input
);
-- End of OBUFTDS_inst instantiation
Verilog Instantiation Template
// OBUFTDS: Differential 3-state Output Buffer
// Versal AI Core series
// Xilinx HDL Language Template, version 2021.1
OBUFTDS OBUFTDS_inst (
.O(O), // 1-bit output: Diff_p output (connect directly to top-level port)
.OB(OB), // 1-bit output: Diff_n output (connect directly to top-level port)
.I(I), // 1-bit input: Buffer input
.T(T) // 1-bit input: 3-state enable input
);
// End of OBUFTDS_inst instantiation
Related Information
- Versal ACAP SelectIO Resources Architecture Manual (AM010)