IDDRE1 - 2021.1 English

Primitive: Dedicated Double Data Rate (DDR) Input Register

PRIMITIVE_GROUP: REGISTER
PRIMITIVE_SUBGROUP: DDR

Introduction

The IDDRE1 I/O Logic primitive in Versal devices is a dedicated input register designed to receive external double data rate (DDR) signals into Xilinx devices. The IDDRE1 is available with modes that present the data to the device fabric at the time and clock edge they are captured, or on the same clock edge. This feature allows you to avoid additional timing complexities and resource usage.

Port Descriptions

Port	Direction	Width	Function
C	Input	1	The high-speed clock input (C) is used to clock in the input serial data stream.
CB	Input	1	The inverted high-speed clock input.
D	Input	1	The serial input data port (D) is the serial (high-speed) data input port of the ISERDESE3. This port accepts data from the IOB or device Fabric.
Q1	Output	1	Registered parallel output 1.
Q2	Output	1	Registered parallel output 2.
R	Input	1	Active-High Asynchronous Reset.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	Yes

Available Attributes

Attribute	Type	Allowed Values	Default	Description
DDR_CLK_EDGE	STRING	"OPPOSITE_EDGE", "SAME_EDGE", "SAME_EDGE_PIPELINED"	"OPPOSITE_EDGE"	Sets the IDDRE1 mode of operation with respect to clock edge. "OPPOSITE_EDGE": Traditional input DDR solution. Data presented to Q1 on the rising edge and Q2 on the falling edge. "SAME_EDGE": Data is presented to the device logic on the same clock edge. Has separated effect. "SAME_EDGE_PIPELINED": Data is presented to the device logic on the same clock edge. Removes the separated effect but incurs clock latency.
IS_CB_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether the clock CB pin is active-High or active-Low.
IS_C_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether the clock C pin is active-High or active-Low.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- IDDRE1: Dedicated Double Data Rate (DDR) Input Register
--         Versal AI Core series
-- Xilinx HDL Language Template, version 2021.1

IDDRE1_inst : IDDRE1
generic map (
   DDR_CLK_EDGE => "OPPOSITE_EDGE", -- IDDRE1 mode (OPPOSITE_EDGE, SAME_EDGE, SAME_EDGE_PIPELINED)
   IS_CB_INVERTED => '0',           -- Optional inversion for CB
   IS_C_INVERTED => '0'             -- Optional inversion for C
)
port map (
   Q1 => Q1, -- 1-bit output: Registered parallel output 1
   Q2 => Q2, -- 1-bit output: Registered parallel output 2
   C => C,   -- 1-bit input: High-speed clock
   CB => CB, -- 1-bit input: Inversion of High-speed clock C
   D => D,   -- 1-bit input: Serial Data Input
   R => R    -- 1-bit input: Active-High Async Reset
);

-- End of IDDRE1_inst instantiation

Verilog Instantiation Template


// IDDRE1: Dedicated Double Data Rate (DDR) Input Register
//         Versal AI Core series
// Xilinx HDL Language Template, version 2021.1

IDDRE1 #(
   .DDR_CLK_EDGE("OPPOSITE_EDGE"), // IDDRE1 mode (OPPOSITE_EDGE, SAME_EDGE, SAME_EDGE_PIPELINED)
   .IS_CB_INVERTED(1'b0),          // Optional inversion for CB
   .IS_C_INVERTED(1'b0)            // Optional inversion for C
)
IDDRE1_inst (
   .Q1(Q1), // 1-bit output: Registered parallel output 1
   .Q2(Q2), // 1-bit output: Registered parallel output 2
   .C(C),   // 1-bit input: High-speed clock
   .CB(CB), // 1-bit input: Inversion of High-speed clock C
   .D(D),   // 1-bit input: Serial Data Input
   .R(R)    // 1-bit input: Active-High Async Reset
);

// End of IDDRE1_inst instantiation

Related Information

Versal ACAP SelectIO Resources Architecture Manual (AM010)