Step 3: Using ILA Advanced Trigger Feature to Trigger on an AXI Read Transaction

Step 3: Using ILA Advanced Trigger Feature to Trigger on an AXI Read Transaction - 2020.2 English

Vivado Design Suite Tutorial: Programming and Debugging (UG936)

Document ID

UG936

Release Date

2021-02-26

Version

2020.2 English

In the ILA – hw_ila_1 dashboard, locate the Trigger Mode Settings area and set Trigger mode to ADVANCED_ONLY.
In the Capture Mode Settings area, set the Trigger position to 512.
In the Trigger State Machine area click the Create new trigger state machine link.
In the New Trigger State Machine File dialog box, set the name of the state machine script to txns.tsm.

A basic template of the trigger state machine script is displayed in the Trigger State Machine gadget. Expand the trigger state machine gadget in the ILA dashboard. Copy the script below after line 17 of the state machine script and save the file.

# The "wait_for_arvalid" state is used to detect the start 
# of the read address phase of the AXI transaction which
# is indicated by the axi_arvalid signal equal to '1'
#
state wait_for_arvalid:
    if (design_1_i/system_ila_0/U0/net_slot_0_axi_arvalid == 1'b1) then
      goto wait_for_rready;
    else
      goto wait_for_arvalid;
    endif
#
# The "wait_for_rready" state is used to detect the start 
# of the read data phase of the AXI transaction which
# is indicated by the axi_rready signal equal to '1'
#
state wait_for_rready:
  if (design_1_i/system_ila_0/U0/net_slot_0_axi_rready == 1'b1) then
    goto wait_for_rlast;
  else
    goto wait_for_rready;
  endif

#
# The "wait_for_rlast" state is used to detect the end 
# of the read data phase of the AXI transaction which
# is indicated by the axi_rlast signal equal to '1'.
# Once the end of the data phase is detected, the ILA core
# will trigger.
#
state wait_for_rlast:
  if (design_1_i/system_ila_0/U0/net_slot_0_axi_rlast == 1'b1) then
    trigger;
  else
    goto wait_for_rlast;
  endif

Note: Use the state machine to detect the various phases of an AXI read transaction:

Beginning of the read address phase
Beginning of the read data phase
End of the read data phase

Arm the trigger of the ILA by right-clicking the hw_ila_1 core in the Hardware Manager window and selecting Run Trigger.
In the Trigger Capture Status window, note that the ILA core is waiting for the trigger to occur, and that the trigger state machine is in the wait_for_a_valid state. Note that the pre-trigger capture of 512 samples has completed successfully:
In the Tcl console, run the read transaction that you set up in the previous section of this tutorial.
```
run_hw_axi $rt
```
Note: The ILA core has triggered and the trigger mark is on the sample where the axi_rlast signal is equal to '1', just as the trigger state machine program intended.