- In your C: drive, create a folder called /Vivado_Debug.
- Download the Reference Design Files from the
Xilinx website.CAUTION:The tutorial and design files may be updated or modified between software releases. You can download the latest version of the material from the Xilinx website.
- Unzip the tutorial source file to the /Vivado_Debug folder. There are six labs that use different methodologies for debugging your design. Select the appropriate lab and follow the steps to complete them.
- Lab 1
- This lab walks you through the steps of marking nets for debug in HDL as
well as the post-synthesis netlist (netlist insertion method). Following are
the required files:
- debounce.vhd
- fsm.vhd
- sinegen.vhd
- sinegen_demo.vhd
- sine_high/sine_high.xci
- sine_low/sine_low.xci
- sine_mid/sine_mid.xci
- sinegen_demo_kc705.xdc
- Lab 2
- This lab goes over the details of marking nets for debug in
the source HDL (HDL instantiation method) as well as instantiating an ILA
core in the HDL. Following are the required files:
- debounce.vhd
- fsm.vhd
- sinegen.vhd
- sinegen_demo_inst.vhd
- ila_0/ila_0.xci
- sine_high/sine_high.xci
- sine_low/sine_low.xci
- sine_mid/sine_mid.xci
- sinegen_demo_kc705.xdc
- Lab 3
- You can test your design even if the hardware is not
physically accessible, using a VIO core. This lab walks you through the
steps of instantiating and customizing a VIO core that you will hook to the
I/Os of the design. Following are the required files:
- debounce.vhd
- fsm.vhd
- sinegen.vhd
- sinegen_demo_inst_vio.vhd
- sine_high/sine_high.xci
- sine_low/sine_low.xci
- sine_mid/sine_mid.xci
- ila_0/ila_0.xci
- sinegen_demo_kc705.xdc
- Lab 4
- Nets can also be marked for debug in a third-party synthesis
tool using directives for the synthesis tool. This lab walks you through the
steps of marking nets for debug in the Synplify tool and then using
Vivado®
to perform the rest of the debug.
Following are the required files:
- debounce.vhd
- fsm.vhd
- sign_high.dcp
- sign_low.dcp
- sine_mid.dcp
- sine_high.xci
- sine_low.xci
- sine_mid.xci
- sinegen.edn
- sinegen_synplify.vhd
- synplify_1.sdc
- synplify_1.fdc
- sinegen_demo_kc705.xdc
- Lab 5
- Take designs created from Lab 1, Lab 2, Lab 3, and Lab 4 and load them onto the KC705 board.
- Lab 6
- Enhance post implementation debugging by using the ECO flow to replace debug probes.
- Lab 7
- Use the Incremental Compile flow to enable faster debugging flows. Using the results from a previous implementation run, this flow allows you to make debug modifications and rerun implementation.
- Lab 8
- Debug high-speed serial I/O links using the Vivado Serial I/O Analyzer. This lab uses the Vivado IP example design.
- Lab 9
- Use Vivado ILA core to debug JTAG-to-AXI transactions. This lab uses the Vivado IP example design.
- Lab 10
- Use the IBERT UltraScale+ PS-GTR transceiver to evaluate and monitor PS-GTR transceivers in Zynq® UltraScale+™ MPSoC devices. This lab is purely software-based, setting up and testing the processing system (PS) side of the Zynq UltraScale+ MPSoC device with no programmable logic (PL).