Adding Debug Nets to the Project - 2020.2 English

Vivado Design Suite Tutorial: Programming and Debugging (UG936)
Document ID
UG936
Release Date
2021-02-26
Version
2020.2 English
Following are some ways to add debug nets using the Vivado IDE:
  • Add MARK_DEBUG attribute to HDL files.
    VHDL
    attribute mark_debug : string; 
attribute mark_debug of sine     : signal is "true";
attribute mark_debug of sineSel  : signal is "true";
    Verilog
    (* mark_debug = "true" *) wire sine;
(* mark_debug = "true" *) wire sineSel;

    This method lets you probe signals at the HDL design level. This can prevent optimization that might otherwise occur to that signal. It also lets you pick up the signal tagged for post synthesis, so you can insert these signals into a debug core and observe the values on this signal during FPGA operation. This method gives you the highest probability of preserving HDL signal names after synthesis.

  • Right-click and select Mark Debug or Unmark Debug on a synthesized netlist.

    This method is flexible because it allows probing the synthesized netlist in the Vivado IDE and allows you to add/remove MARK_DEBUG attributes at any hierarchy in the design. In addition, this method does not require HDL source modification. However, there can be situations where synthesis might not preserve the signals due to netlist optimization involving absorption or merging of design structures.

  • Use a Tcl prompt to set the MARK_DEBUG attribute on a synthesized netlist.
    set_property mark_debug true [get_nets -hier [list {sine[*]}]]

    This applies the MARK_DEBUG on the current, open netlist.

    This method is flexible because you can turn MARK_DEBUG on and off by modifying the Tcl command. In addition, this method does not require HDL source modification. However, there might be situations where synthesis does not preserve the signals due to netlist optimization involving absorption or merging of design structures.

In the following steps, you learn how to add debug nets to HDL files and the synthesized design using Vivado IDE.

Tip: Before proceeding, make sure that the Flow Navigator on the left panel is enabled.

Use Ctrl-Q to toggle it off and on.

  1. In the Flow Navigator under the Synthesis drop-down list, click Open Synthesized Design as shown in the following figure.

  2. In the Window drop-down menu, select Debug. When the Debug window opens, click the window if it is not already selected.
  3. Expand the Unassigned Debug Nets folder. The following figure shows those debug nets that were tagged with MARK_DEBUG attributes in sinegen_demo.vhd.

  4. In the Netlist window, select the Netlist tab and expand Nets. Select the following nets for debugging as shown in the following figure.
    GPIO_BUTTONS_IBUF[0] and GPIO_BUTTONS_IBUF[1]
    Nets folder under the top-level hierarchy
    sel(2)
    Nets folder under the U_SINEGEN hierarchy
    sine(20)
    Nets folder under the U_SINEGEN hierarchy


    Note: These signals represent the significant behavior of this design and are used to verify and debug the design in subsequent steps.
  5. Right-click the selected nets and select Mark Debug as shown in the following figure.

  6. Next, mark nets for debug in the Tcl console. Mark nets “sine(20)” under the U_SINEGEN hierarchy for debug by executing the following Tcl command.
    set_property mark_debug true [get_nets -hier [list {sine[*]}]]
    Tip: In the Debug window, you can see the unassigned nets you just selected. In the Netlist window, you can also see the green bug icon next to each scalar or bus, which indicates that a net has the attribute mark_debug = true as shown in the following two figures.