Step 2: Synthesize, Implement, and Generate the Bitstream - 2020.2 English

1. From the Program and Debug drop-down list in Flow Navigator, click Generate Bitstream. This synthesizes, implements, and generates a bitstream for the design
2. The Missing Implementation Results dialog box appears. Click OK.
3. After bitstream generation completes, the Bitstream Generation Completed dialog box appears. Open Implemented Design is selected by default. Click OK.
4. Inspect the Timing Summary report and make sure that all timing constraints have been met.
   
   
5. Proceed to Using the Vivado Logic Analyzer to Debug Hardware to complete the rest of the steps for debugging the design. Then proceed to the Verifying the VIO Core Activity (Only Applicable to Lab 3) section in Lab 5 Step 2 to complete the rest of this lab.