The black box, sinegen, created in the Synplify Pro project, contains the Direct Digital
Synthesizer IP. You need to create a synthesized design for this block. To do this,
create an RTL type project in
Vivado®
IDE by following the steps
outlined below.
- Launch Vivado IDE.
- Click Create Project. This opens up the New Project wizard. Click Next.
- Under Project Name, set the project name to proj_synplify_netlist. Click Next.
- Under Project Type, select RTL Project. Click Next.
- Under Add Sources, click Add Files, navigate to the Vivado_Debug/src/lab4 folder and select the sinegen.vhd file. Set Target Language to VHDL. Ensure that Copy sources into project box is selected. Click Next.
- Click Add Files, navigate to the Vivado_Debug/src/lab4 folder and select the sine_high.xci, sine_low.xci, and sine_mid.xci files. Click Next.
- Under Default Parts, select Boards and then select the Kintex-7 KC705 Evaluation Platform and correct version for your hardware. Click Next.
- Under New Project Summary, ensure that all the settings are correct. Click Finish.
- Once the project has been created, in Vivado Flow Navigator, under the Project Manager folder, click Settings. In the dialog box, in the left panel, click Synthesis. From the pull-down menu on the right panel, set -flatten_hierarchy to none. Click OK.
- In Vivado IDE Flow Navigator, under Synthesis Folder, click Run Synthesis.
- When synthesis completes the Synthesis Completed dialog box appears. Select Open Synthesized Design and click OK.
- Click in Vivado IDE. When the OK to exit dialog box pops up, click OK.