System Architecture - 2020.2 English

Versal ACAP Design Guide (UG1273)

Document ID
Release Date
2020.2 English

The Xilinx® Versal™ ACAP is a collection of programmable resources that work together to form a system on chip (SoC). Following are the major resource blocks:

  • AI Engine
    Note: AI Engine availability is device specific.
  • Programmable logic (PL)
  • Network on chip (NoC)
  • High-speed I/O (XPIO)
  • Integrated memory controllers LPDDR4 and DDR4 (DDRMC)
  • Processing system (PS)
  • Platform management controller (PMC)
  • Integrated block for PCIe® with DMA and cache coherent interconnect (CPM)
    Note: CPM availability is device specific.
  • Transceivers (GT)
  • High-speed debug port (HSDP)
  • Multirate Ethernet MAC (MRMAC)

Versal ACAP applications can exploit the capabilities of each of these resources. To create or migrate a design to a Versal ACAP, you must identify which resources best satisfy the different needs of the application and partition the application across those resources.

The following figure shows the layout of the Versal ACAP.

Figure 1. Versal ACAP Layout

The following sections provide a summary of the blocks that comprise the Versal architecture. For detailed information on these blocks, see the Versal Architecture and Product Data Sheet: Overview (DS950).