Subsystem Design Flow - 2020.2 English

Versal ACAP Design Guide (UG1273)

Document ID
Release Date
2020.2 English

Prior to starting development, you must choose the Versal device that is best suited for your application and partition the design into functions targeted to the PS, AI Engine, and PL, depending on the application requirements. At this point, you must have an understanding of the following:

  • System design considerations, such as throughput and latency
  • Domain and inter-domain capabilities, including compute and bandwidth
  • Dataflow and control flow throughout the entire system and the various subsystems

In addition, you must consider the type of platform to target. You must plan and design for the peripherals and interfaces on the board and the memory resources available on your custom board.

The following figure shows a subsystem that targets a custom hardware platform.

Figure 1. Custom Hardware Platform Subsystem

The Vitis design flow is an iterative process that might loop through each step multiple times, adding layers or elements to the subsystem through subsequent iterations. Teams can iterate through the early steps more quickly and take more time with later steps, which provide more detailed performance data.

Following are the recommended steps for creating your design in the Vitis environment.

Kernel and Graph Development
This step includes the development and functional verification of application kernels. These kernels can run on the AI Engine domain or the PL domain.
Subsystem Assembly and Verification Using Hardware Emulation
This step includes assembling the AI Engine and PL kernels with the platform as well as building for hardware emulation using a Xilinx standard platform.
Subsystem Assembly and Verification on Hardware
This step includes building the subsystem against the Xilinx standard platform and testing in real hardware on a Xilinx standard board.
Subsystem Integration on Custom Platform
This step includes building the subsystem against your custom platform and testing using your custom board.

The Vitis environment design flow makes a distinction between platforms and subsystems, which insulates subsystem developers from internal platform details and allows them to build fully functional designs independently. The first three steps of the subsystem design flow assume you are using Xilinx-provided platforms and you are integrating the subsystem to your custom platform in the final step. The custom platform is developed using the Vivado Design Suite and can happen in parallel with the subsystem, which is developed using the Vitis tool flow. This approach reduces risk and uncertainty and increases the chances of success when integrating the subsystem with the custom platform.