Platform-Based Design Flows - 2020.2 English

Versal ACAP Design Guide (UG1273)

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2020.2 English

In the platform-based design flow, the hardware design is conceptually divided in two distinct elements: a platform and the processing subsystem. The platform contains essential Versal IP blocks (including CIPS, NoC, AI Engine, and Clocking Wizard) and board interface IP blocks (including high-speed I/Os and memory controllers). The processing subsystem contains the application-specific part of the system and can be composed of both programmable logic and AI Engine blocks. The platform is considered extensible, because the platform does not contain the entirety of the programmable logic content. Instead, the platform is extended by the addition of the processing subsystem.

Following are the main steps in this flow:

  1. Create the hardware platform using the Vivado IP integrator and RTL code.
  2. Create the processing subsystem using the Vitis tools.
  3. Integrate the acceleration subsystem with the platform using the Vitis linker to create a fixed hardware design that is implemented using the Vivado tools.
  4. Develop the software application on top of the fixed hardware design using the Vitis embedded software development flow.
  5. When using the Versal AI Core series, develop the AI Engine program as part of the processing subsystem.
Important: This is the only flow that supports programming of the AI Engine cores and is therefore required for Versal AI Core devices.
Tip: Xilinx provides off-the-shelf platforms for Versal ACAP evaluation kits, such as the VCK190.