PL Configuration and JTAG - 2020.2 English

Versal ACAP Design Guide (UG1273)

Document ID
Release Date
2020.2 English

The Versal architecture differs from previous architectures for boot and configuration. The PL configuration and JTAG standalone primitives are not supported in Versal ACAP but similar capability exists as follows:

  • The BSCANE2 primitive is replaced by four JTAG TAP user instructions available in the CIPS IP.
  • The STARTUPE3 primitive is replaced by the combination of the QSPI controller MIO and CIPS IP (global asynchronous set/reset signal, global 3-state, end of startup (EOS) signal, PL clocks (PL0-PL3) source configuration).
  • The DNA_PORTE2 primitive is replaced by the JTAG DNA register or AXI memory mapped accessible 32-bit registers DNA_0, DNA_1, DNA_2, and DNA_3 to read out the device DNA.
  • The EFUSE_USR primitive is replaced by the AXI memory mapped EFUSE_CACHE registers.

For more information on the memory mapped registers, including address mapping, see the Versal ACAP Technical Reference Manual (AM011) and the Versal ACAP Register Reference (AM012).