References - 2020.2 English

Versal ACAP Design Guide (UG1273)
Document ID
UG1273
Release Date
2021-03-26
Version
2020.2 English

These documents provide supplemental material useful with this guide:

  1. Versal Architecture and Product Data Sheet: Overview (DS950)
  2. Extending the Thermal Solution by Utilizing Excursion Temperatures (WP517)
  3. Versal ACAP GTY and GTYP Transceivers Architecture Manual (AM002)
  4. Versal ACAP Clocking Resources Architecture Manual (AM003)
  5. Versal ACAP DSP Engine Architecture Manual (AM004)
  6. Versal ACAP Configurable Logic Block Architecture Manual (AM005)
  7. Versal ACAP System Monitor Architecture Manual (AM006)
  8. Versal ACAP Memory Resources Architecture Manual (AM007)
  9. Versal ACAP AI Engine Architecture Manual (AM009)
  10. Versal ACAP SelectIO Resources Architecture Manual (AM010)
  11. Versal ACAP Technical Reference Manual (AM011)
  12. Versal ACAP Register Reference (AM012)
  13. Versal ACAP Packaging and Pinouts Architecture Manual (AM013)
  14. Versal ACAP CPM CCIX Architecture Manual (AM016)
  15. SmartConnect LogiCORE IP Product Guide (PG247)
  16. Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)
  17. Versal Devices Integrated 100G Multirate Ethernet MAC (MRMAC) LogiCORE IP Product Guide (PG314)
  18. Advanced I/O Wizard LogiCORE IP Product Guide (PG320)
  19. Versal ACAP Transceivers Wizard LogiCORE IP Product Guide (PG331)
  20. Versal ACAP Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)
  21. Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
  22. Versal ACAP PCIe PHY LogiCORE IP Product Guide (PG345)
  23. Versal ACAP CPM Mode for PCI Express Product Guide (PG346)
  24. Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)
  25. Control, Interface and Processing System LogiCORE IP Product Guide (PG352)
  26. Versal ACAP Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)
  27. Versal ACAP Soft RLDRAM 3 Memory Controller LogiCORE IP Product Guide (PG354)
  28. Versal ACAP Soft QDR-IV SRAM Memory Controller LogiCORE IP Product Guide (PG355)
  29. AI Engine LogiCORE IP Product Guide (PG358)
  30. Versal ACAP PCB Design User Guide (UG863)
  31. Vivado Design Suite User Guide: System-Level Design Entry (UG895)
  32. Vivado Design Suite User Guide: Logic Simulation (UG900)
  33. Vivado Design Suite User Guide: Synthesis (UG901)
  34. Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)
  35. Vivado Design Suite User Guide: Programming and Debugging (UG908)
  36. Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)
  37. Vivado Design Suite: AXI Reference Guide (UG1037)
  38. Versal ACAP AI Engine Programming Environment User Guide (UG1076)
  39. Versal ACAP AI Engine Kernel Coding User Guide (UG1079)
  40. Xilinx Power Estimator User Guide for Versal ACAP (UG1275)
  41. Bootgen User Guide (UG1283)
  42. Versal ACAP System Software Developers Guide (UG1304)
  43. Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)
  44. Versal ACAP System Integration and Validation Methodology Guide (UG1388)
  45. XRT Release Notes (UG1451)
  46. Model Composer and System Generator User Guide (UG1483)
  47. Versal ACAP System and Solution Planning Methodology Guide (UG1504)
  48. Versal ACAP Board System Design Methodology Guide (UG1506)
  49. Seven Steps to an Accurate Worst-Case Power Analysis using the Xilinx Power Estimator (XAPP1348)
  50. Versal ACAP Schematic Review Checklist (XTP546)
  51. Versal ACAP External Memory Pre-Planning Tool (XTP667)
  52. AI Engine SystemC Simulator in the AI Engine Documentation flow of the Vitis Unified Software Platform Documentation (UG1416)
  53. Bootgen Tool in the Embedded Software Development flow of the Vitis Unified Software Platform Documentation (UG1416)
  54. Debugging the AI Engine Application in the AI Engine Documentation flow of the Vitis Unified Software Platform Documentation (UG1416)
  55. Packaging the System in the AI Engine Documentation flow of the Vitis Unified Software Platform Documentation (UG1416)
  56. Programming the PS Host Application in the AI Engine Documentation flow of the Vitis Unified Software Platform Documentation (UG1416)
  57. RTL Kernels in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416)
  58. Vitis Accelerated Software Development Flow Documentation in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416)
  59. Vitis HLS Documentation in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416)
  60. Vitis Unified Software Platform Documentation (UG1416)