The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 03/26/2021 Version 2020.2 | |
| System Planning | Moved content to Versal ACAP System and Solution Planning Methodology Guide (UG1504). |
| System Design Types | Added new section. |
| Design Flows | Updated with information on traditional and platform-based design flows. |
| 02/04/2021 Version 2020.2 | |
| Application Mapping and Design Partitioning | Added sections on design partitioning. |
| Debug Interfaces | Added new section. |
| Design Closure | Added details on design closure. |
| Logic Simulation Using SystemC Models | Added new section. |
| MRMAC | Added new section. |
| Security | Updated table. |
| 12/04/2020 Version 2020.2 | |
| NoC | Added information the NPI. |
| Design Flows | Updated with information on the main design flows and Versal™ ACAP support for each. |
| Vivado Tools Design Flow | Updated information on the block design flow and RTL design flow. |
| I/O Planning | Added information on MIO and EMIO. |
| Power Closure | Added new section. |
| Simulation Flows | Moved to Vitis™ Environment Design Flow section. |
| Boot Image Generation | Added commands for PDI generation. |
| GT | Added information on block automation. |
| Power and Error Handling | Added information on power islands. |
| PCIe Subsystems | Updated migration information. |
| Boot and Configuration | Moved to System Migration chapter. |
| Clocking | Added new section. |
| Primitives | Added VHDL examples. |
| Block RAM Primitives | Added information on XPM inference. |
| UltraRAM Primitives | Added information on XPM inference. |
| Coding Style and Primitive Instantiation Examples | Added new section. |
| 07/14/2020 Version 2020.1 | |
| Initial release | N/A |