Using the Netlist Insertion Method to Debug a Design - 2024.1 English

Vivado Design Suite Tutorial: Programming and Debugging (UG936)

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2024.1 English

In this lab, you mark signals for debugging in the source HDL and the post-synthesis netlist. You can create an Integrated Logic Analyzer (ILA) core and take the design through implementation. Finally, you use the AMD Vivado™ tool to connect to the KC705 target board and debug your design with the Vivado Integrated Logic Analyzer.