Using the Netlist Insertion Method to Debug a Design - 2024.1 English

Vivado Design Suite Tutorial: Programming and Debugging (UG936)

Document ID
UG936
Release Date
2024-06-12
Version
2024.1 English

In this lab, you mark signals for debugging in the source HDL and the post-synthesis netlist. You can create an Integrated Logic Analyzer (ILA) core and take the design through implementation. Finally, you use the AMD Vivado™ tool to connect to the KC705 target board and debug your design with the Vivado Integrated Logic Analyzer.