Objectives - 2024.1 English

Vivado Design Suite Tutorial: Programming and Debugging (UG936)

Document ID
UG936
Release Date
2024-06-12
Version
2024.1 English

These tutorials:

  • Show you how to take advantage of integrated Vivado logic analyzer features in the Vivado design environment that makes the debug process faster and simpler.
  • Provide specifics on how to use the Vivado IDE and the Vivado logic analyzer to debug common problems in FPGA logic designs.
  • Provide specifics on how to use the Vivado Serial I/O Analyzer to debug high-speed serial links.

After completing this tutorial, you are able to:

  • Validate and debug your design using the Vivado Integrated Design Environment (IDE) and the Integrated Logic Analyzer (ILA) core.
  • Understand how to create an RTL project, probe your design, insert an ILA core, and implement the design in the Vivado IDE.
  • Generate and customize an IP core netlist in the Vivado IDE.
  • Debug the design using Vivado logic analyzer in real-time and iterate the design using the Vivado IDE and a KC705 Evaluation Kit Base Board that incorporates an AMD Kintex™ 7 device.
  • Analyze high-speed serial links using the Serial I/O Analyzer.