- Launch Synplify Pro and select .
- Set File Type to Project File (Project) as highlighted in the following figure.
- In the New File Name box, enter synplify_1.
- Click OK.
- If you get a dialog box asking you to create a non-existing directory, click
OK.
- In the left panel of the Synplify Pro window, click Add File as shown in the following figure.
- In the Add Files to Project dialog box, change the Files of Type to HDL File.
Navigate to C:\Vivado_Debug\src\lab4, which shows all the
VHDL source files needed for this lab. Select the following three files by
pressing the Ctrl key and clicking on them.
- debounce.vhd
- fsm.vhd
- sinegen_demo.vhd
- Click Add.
- In the same dialog box, set Files of type to Constraints Files. This shows
the synplify_1.sdc file. Select the file
and click Add as shown in the following
figure.
- In the same dialog box, set Files of type to FPGA Constraint Files. This
shows the synplify_1.fdc file. Select the file and click Add as shown in the following figure. Click
OK.
- Now, you need to set the implementation options.
- Click Implementation Options in the
Synplify Pro window, as shown in the following figure.