Using FSBL with Serial I/O Analyzer to Bring Up IBERT PS-GTR - 2024.1 English

Vivado Design Suite Tutorial: Programming and Debugging (UG936)

Document ID
UG936
Release Date
2024-06-12
Version
2024.1 English
  1. Connect all the physical devices such as SATA Drive, PCIe® card, and USB device based on your selection from the four valid GT configurations for ZCU102 prior to loading the FSBL. Hot swap or hot plug is not supported.
  2. Open Vivado.
  3. Open hardware manager and connect to a board with a Zynq UltraScale+ device. The following example shows connecting to a board on a remote machine, so hw_server needs to be running on the remote machine before it can connect.

  4. Verify the ARM_DAP is visible in the hardware device list and click Next, and click Finish.

  5. Right-click the ARM_DAP device in the hardware tree and select Configure IBERT GTR.

  6. When the dialog box opens, you must provide the FSBL ELF file created in the previous steps and optionally a configuration file (a bitstream, if your design requires one). You can also reset the system before configuring with the Reset Zynq option checked. Click OK when done.
    Note: The Reset Zynq option leaves the ARM_DAP in a bad state on early versions of Zynq UltraScale+ devices (for example, ZU9EG es1). If that occurs, power cycle the board and keep the Reset Zynq option unchecked.


  7. config_hw_sio_gts is executed with the selected settings. refresh_hw_device is called to rescan the device for new debug cores. The IBERT should be configured as shown in the following example.

  8. The Auto-detect links option does not work for PS-GTR. You can manually create links by using Create Links as shown in the following figure.

  9. Create links for all four lanes with each lane’s TX connected to the same lane’s RX, as shown in the following figure.

    Click OK when done.



  10. The following figure shows the Serial I/O Links view where Status shows all the four lanes as linked.

    Note: The Link 1 PLL Status shows Not Locked, because it uses the Link 0 PLL as required by PCIe protocol.
  11. Right-click on any link and select Create Scan.

  12. Select the appropriate parameters for EyeScan and perform the EyeScan. For example, the following figure is performing EyeScan on Lane L1 (Link 1). Once the EyeScan completes, the eye from -1UI to +1UI is displayed.
    Note: Although the Create Scan pop up shows -0.5UI to +0.5UI, the EyeScan displayed is from -1UI to +1UI.


  13. The following figure is a sample EyeScan performed on Lane L1.

    Note: The value reported by Open UI % is a percentage of the entire horizontal axis, which is 2UI wide for the PS-GTR transceiver.