Interfaces and Ports - 2.0 English

The following table shows the AXI4 instruction and data cache interface ports of the MCU.

Table 1. MCU Ports
Port	Size (bits)	Direction	Description
vdu_pl_mcu_m_axi_araddr	64	Output	AXI4 read address
vdu_pl_mcu_m_axi_arburst	2	Output	AXI4 read burst type
vdu_pl_mcu_m_axi_arcache	4	Output	AXI4 ARCACHE value
vdu_pl_mcu_m_axi_arid	18	Output	AXI4 read master ID
vdu_pl_mcu_m_axi_arlen	8	Output	AXI4 read burst size
vdu_pl_mcu_m_axi_arlock	1	Output	AXI4 ARLOCK signal
vdu_pl_mcu_m_axi_arprot	3	Output	AXI4 ARPROT signal
vdu_pl_mcu_m_axi_arqos	4	Output	AXI4 ARQOS signal
pl_vdu_mcu_m_axi_arready	1	Input	AXI4 ARREADY signal
vdu_pl_mcu_m_axi_arsize	3	Output	AXI4 ARSIZE signal
vdu_pl_mcu_m_axi_arvalid	1	Output	AXI4 ARVALID signal
vdu_pl_mcu_m_axi_awaddr	64	Output	AXI4 AWADDR signal
vdu_pl_mcu_m_axi_awburst	2	Output	AXI4 AWBURST signal
vdu_pl_mcu_m_axi_awcache	4	Output	AXI4 AWCACHE signal
vdu_pl_mcu_m_axi_awid	18	Output	AXI4 AWID signal
vdu_pl_mcu_m_axi_awlen	8	Output	AXI4 AWLEN signal
vdu_pl_mcu_m_axi_awlock	1	Output	AXI4 AWLOCK signal
vdu_pl_mcu_m_axi_awprot	3	Output	AXI4 AWPROT signal
vdu_pl_mcu_m_axi_awqos	4	Output	AXI4 AWQOS signal
pl_vdu_mcu_m_axi_awready	1	Input	AXI4 AWREADY signal
vdu_pl_mcu_m_axi_awsize	3	Output	AXI4 AWSIZE signal
vdu_pl_mcu_m_axi_awvalid	1	Output	AXI4 AWVALID signal
pl_vdu_mcu_m_axi_bid	18	Input	AXI4 BID signal
vdu_pl_mcu_m_axi_bready	1	Output	AXI4 BREADY signal
pl_vdu_mcu_m_axi_bresp	2	Input	AXI4 BRESP signal
pl_vdu_mcu_m_axi_bvalid	1	Input	AXI4 BVALID signal
pl_vdu_mcu_m_axi_rdata	32	Input	AXI4 RDATA signal
pl_vdu_mcu_m_axi_rid	18	Input	AXI4 RID signal
pl_vdu_mcu_m_axi_rlast	1	Input	AXI4 RLAST signal
vdu_pl_mcu_m_axi_rready	1	Output	AXI4 RREADY signal
pl_vdu_mcu_m_axi_rresp	2	Input	AXI4 RRESP signal
pl_vdu_mcu_m_axi_rvalid	1	Input	AXI4 RVALID signal
vdu_pl_mcu_m_axi_wdata	32	Output	AXI4 WDATA signal
vdu_pl_mcu_m_axi_wlast	1	Output	AXI4 WLAST signal
pl_vdu_mcu_m_axi_wready	1	Input	AXI4 WREADY signal
vdu_pl_mcu_m_axi_wstrb	4	Output	AXI4 WSTRB signal
vdu_pl_mcu_m_axi_wvalid	1	Output	AXI4 WVALID signal
vdu_pl_mcu_m_axi_arregion	4	Output	AXI4 ARREGION signal
vdu_pl_mcu_m_axi_aruser	16	Output	AXI4 ARUSER signal
vdu_pl_mcu_m_axi_awregion	4	Output	AXI4 AWREGION signal
vdu_pl_mcu_m_axi_awuser	16	Output	AXI4 AWUSER signal
pl_vdu_mcu_m_axi_buser	16	Input	AXI4 BUSER signal
pl_vdu_mcu_m_axi_ruser	16	Input	AXI4 RUSER signal
vdu_pl_mcu_m_axi_wuser	16	Output	AXI4 WUSER signal

The following table summarizes the AXI4-Lite slave interface ports of the MCU subsystem.

Table 2. AXI4-Lite Slave Ports
Port	Width	Direction	Description
pl_vdu_awaddr_axi_lite_apb	23	Input	AXI4 AWADDR signal
pl_vdu_awprot_axi_lite_apb	3	Input	AXI4 AWPROT signal
pl_vdu_awvalid_axi_lite_apb	1	Input	AXI4 AWVALID signal
vdu_pl_awready_axi_lite_apb	1	Output	AXI4 AWREADY signal
pl_vdu_wdata_axi_lite_apb	32	Input	AXI4 WDATA signal
pl_vdu_wstrb_axi_lite_apb	4	Input	AXI4 WSTRB signal
pl_vdu_wvalid_axi_lite_apb	1	Input	AXI4 WVALID signal
vdu_pl_wready_axi_lite_apb	1	Output	AXI4 WREADY signal
vdu_pl_bresp_axi_lite_apb	2	Output	AXI4 BRESP signal
vdu_pl_bvalid_axi_lite_apb	1	Output	AXI4 BVALID signal
pl_vdu_bready_axi_lite_apb	1	Input	AXI4 BREADY signal
pl_vdu_araddr_axi_lite_apb	23	Input	AXI4 ARADDR signal
pl_vdu_arprot_axi_lite_apb	3	Input	AXI4 ARPROT signal
pl_vdu_arvalid_axi_lite_apb	1	Input	AXI4 ARVALID signal
vdu_pl_arready_axi_lite_apb	1	Output	AXI4 ARREADY signal
vdu_pl_rdata_axi_lite_apb	32	Output	AXI4 RDATA signal
vdu_pl_rresp_axi_lite_apb	2	Output	AXI4 RRESP signal
vdu_pl_rvalid_axi_lite_apb	1	Output	AXI4 RVALID signal
pl_vdu_rready_axi_lite_apb	1	Input	AXI4 RREADY signal