General Design Guidelines - 2023.2 English

H.264/H.265 Video Decode Unit Solutions LogiCORE IP Product Guide (PG414)

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2023.2 English

The Video Decode Unit core is an embedded hard IP in AMD Versalâ„¢ Adaptive SoC (Versal AI Edge and Versal AI Core Series). All interfaces are connected through AXI interconnect blocks in the PL. The VDU core is AXI4 compliant on its AXI master interfaces. It can be connected to the slave ports of Versal NoC hard block which is connected to DDR memory controller. There are no direct (hardwired) connections from the VDU to the processing system (PS).

The register programming interface of the VDU core connects to PS Master ports (M_AXI_FPD or M_AXI_LPD). The VDU core clock can be used from PL or through an internal PLL inside the VDU core.