The following tables summarizes the signals that are either shared by, or are not a part of the dedicated AXI4 interfaces.
| Port Name | Direction | Description |
|---|---|---|
| s_axi_lite_aclk | Input | AXI clock input for S_AXI_PL_VDU_LITE |
| ref_clk | Input | Reference clock input |
| vdu_resetn | Input | Active-Low reset input from PL |
| vdu_host_interrupt | Output | Active-High interrupt output from VDU. Can be mapped to PL- PS interrupt pin. |
| m_axi_dec_aclk | Input | AXI input clock for M_AXI_VDU_DECODER0 and M_AXI_VDU_DECODER1 |
| m_axi_mcu_aclk | Input | Input clock for M_AXI_MCU interface |