DPLL Overview - 2023.2 English

H.264/H.265 Video Decode Unit Solutions LogiCORE IP Product Guide (PG414)

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2023.2 English

The VDU core uses in-built DPLL for generating the following clocks:

  • VDU Decoder core clock (upto 800 MHz)
  • VDU MCU clock (upto 571 MHz)

The AMD Vivado™ wrapper for VDU should handle programming of DPLL to get the required clocks. This programming is static.