Core Overview - 2023.2 English

H.264/H.265 Video Decode Unit Solutions LogiCORE IP Product Guide (PG414)

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2023.2 English

The H.264/H.265 Video Decode Unit AMD LogiCOREā„¢ (VDU) IP core supports multi-standard video decoding, including support for the High Eficiency Video Coding (HEVC) and Advanced Video Coding (AVC) H.264 standards. The unit contains decode (decompress) functions.

The VDU is an integrated block containing decoder interfaces located in the programmable logic (PL) portion of the Versal adaptive SoC (Versal AI Edge series and Versal AI Core series) devices. Located in the programmable logic (PL), the VDU does not have any direct connections to the processing system (PS).

VDU operation requires the application processing unit (APU) as a controller to service interrupts and coordinate data transfer.

The decoder is controlled by the APU through a task list prepared in advance, and the APU response time is not in the execution critical path. The VDU has no audio support. You can execute audio decoding in the software using the PS or through soft IP in the PL. The following figure shows the top-level block diagram with one instance of VDU core.

Figure 1. Top-Level Block Diagram of Single Instance Decoder Block