Clocking - 2023.2 English

H.264/H.265 Video Decode Unit Solutions LogiCORE IP Product Guide (PG414)

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2023.2 English

The following table describes the clock domains in the VDU core.

Table 1. VDU Clock Domains
Domain Max Freq (MHz) Description
Core clock 800 Processing core, most of the logic and memories
MCU clock 571 Internal micro controllers
AXI Master Port clock 400



AXI master port for memory access, 128-bit, typically connected to PS AFI-FM (HP) port or to a soft memory controller in the PL

AXI4-Lite slave port clock 167 s_axi_lite_aclk, AXI4-Lite slave port (32-bit) for register programming
NPI Clock 300 NPI interface clock
Note: All AXI clocks are supplied with clocks from external PL/PS sources. All primary clocks in VDU are asynchronous to each other.
The following figure shows the clock generation options inside VDU block.
Note: The following blocks work on a single clock domain:
  • pll_ref_clk is sourced externally to the device, typically by a programmable clock integrated circuit.
  • Video decoder blocks work under the core_clk domain generated by the DPLL.
  • MCU for decoder work under the MCU_clk domain generated by the DPLL.
  • m_axi_dec_aclk is the AXI clock input from the PL for the 128-bit AXI master interfaces for the decoder.
  • s_axi_lite_aclk is the AXI4-Lite clock from the PL and PS.
  • m_axi_mcu_aclk is the MCU AXI master clock from the PL.
Note: The following blocks work on a single clock domain.
Figure 1. Clock Generation Options

The following clock frequency requirements must be met while providing clocks from PL:

  • The AXI clock for decoder interface is limited to 400 MHz.
  • The following ratio requirements need to be met:
    • s_axi_lite_aclk ≤ 2 × m_axi_dec_aclk

Refer to Microcontroller Unit Overview for more information on the MCU.

The core_clk is generated based on the VDU DPLL.

The mcu_clk is generated based on the VDU DPLL.