HDMI 2.1 Receiver - 1.2 English

HDMI 2.1 Receiver Subsystem v1.2 Product Guide (PG351)

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1.2 English
Figure 1. HDMI 2.1 RX Subsystem Core Block Diagram

The HDMI 2.1 RX Subsystem is connected to an AMD HDMI PHY Controller /HDMI GT Subsystem, which takes electronic signals from an HDMI cable and translates it into HDMI stream. Then, the HDMI RX core converts the HDMI stream into native video stream and AXI4-Stream audio stream. The Video In to AXI4-Stream bridge converts the video stream taken from the HDMI 2.1 Receiver core into AXI4-Stream.

The HDMI 2.1 RX Subsystem supports both Transition Minimized Differential Signaling (TMDS) and Fixed Rate Link (FRL) protocol based on the HDMI source capability connected. You can build an HDMI 2.1 sink system using the HDMI 2.1 RX Subsystem, and its capability is declared in the customized Extended Display Identification Data (EDID).

The HDMI 2.1 Receiver sub-core contains two separate data paths. One is to decode the video stream TMDS signal, the other is to decode the incoming 16-bit/18-bit encoded data, scramble them, mapping them into FRL packets, removing FEC parity, depacketize them into the video stream, then sending to HDMI 2.0 logic for video format decoding. A data multiplexer is used to select TMDS or FRL received from the PHY layer. The PHY layer is controlled by the HDMI PHY Controller /HDMI GT Subsystem, which is capable of supporting both TMDS and FRL (at rate up to 12 Gbps).