General Checks - 1.2 English

HDMI 2.1 Receiver Subsystem v1.2 Product Guide (PG351)

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1.2 English
  • Ensure that all the timing constraints and all other constraints were met during implementation.
  • Ensure that all clock sources are active and clean.
  • If using MMCMs in the design, ensure that all MMCMs have obtained lock by monitoring the locked port.
  • If your outputs go to 0, check your licensing.
    • User LEDs (ZCU102/ZCU106/VCU118/VCK190/VEK280)
    • LED0 - HDMI 2.1 RX Subsystem lock (when the HDMI Example Design is used)
    • Use the debug port to check if there are link data driven to the HDMI PHY Controller /HDMI GT Subsystem core.
    • See the Debugging Appendix in the HDMI PHY Controller LogiCORE IP Product Guide (PG333) / HDMI GT Controller LogiCORE IP Product Guide (PG334) , and ensure there is no problem with clocking issues.