HDMI 2.1 Receiver Subsystem v1.2 Product Guide (PG351)

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1.2 English

This interrupt is triggered every time FRL Training state for rate change is successfully executed.

The callback function must perform the following steps:

  1. Update the application to configure the clock for the RX source.
  2. Enable the differential input clock buffer.
    void XHdmiphy1_IBufDsEnable(XHdmiphy1 *InstancePtr,
     u8 QuadId,
     XHdmiphy1_DirectionType Dir,
     u8 Enable)
  3. Configure the PHY GT for HDMI 2.1 operation.
    u32 XHdmiphy1_Hdmi21Config(XHdmiphy1 *InstancePtr,
        u8 QuadId,
    XHdmiphy1_DirectionType Dir,
    u64 LineRate,
    u8 NChannels)


    • InstancePtr is a pointer to the XVphy core instance.
    • QuadId is the GT quad ID to operate on.
    • Dir is an indicator for TX or RX.
    Note: QuadId is not used and should be set to 0.

4. Set the video clock for the RX core FRL peripheral to 0.

XV_HdmiRx1_SetFrlVidClock(InstancePtr, Value)