Product Specification - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)

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1.0 English

Clocking Wizard helps create the clocking circuit for the required output clock frequency, phase and duty cycle using mixed-mode clock manager (MMCM) or phase-locked loop (XPLL/DPLL) primitive. It also helps verify the generated output clock frequency in simulation, providing a synthesizable example design which can be tested on the hardware.

The functional block diagram of the core is shown in the following figure.

Figure 1. Core Block Diagram