Auto Buffer Selection and Clock Grouping - Auto Buffer Selection and Clock Grouping - 1.0 English

In Auto mode (the clock out drives set to "Buffer"), all those clock outs must be driven through one of the buffers (the buffer can be BUFG or MBUFGCE).
In Auto mode (the clock out drives set to "Buffer with CE"), all the clock outs are driven through one of the buffers with CE input (BUFGCE or MBUFGCE).
The IP considers all the clock outs where drives selected as "Buffer" or "Buffer with CE" into auto buffer criteria and which buffer driven through is chosen optimally based on other settings provided by you.
MBUFGCE is inferred if the clock outs have frequencies as /1, /2, /4, and /8 in addition to phase set to 0 degree and duty cycle set to 50 percent and all those clock out to be under same clock group.
Each clock out are provided with five clock group options to choose from:
- Auto (default option)
- CLOCK_A
- CLOCK_B
- CLOCK_C
- None
Auto clock grouping means you do not want to provide any clock grouping explicitly, but IP makes the clocks into separate groups optimally depending on the MBUFGCE inference
At max three, MBUFGCE be inferred as auto buffer (as at max seven clocks are present, each MBUFGCE inference to have at least two clocks)
For all the clocks selected with an explicit clock grouping, irrespective of auto buffer selection, are grouped together, and the constraints generate (CLOCK_DELAY_GROUP constraints generate in <ip>.xdc file)
The following are example combinations with auto buffer (drives selected as "Buffer") and auto clock grouping:
1. When all the frequencies are independent to each other (no integer division between any of them) then all clock outs are inferred with separate BUFG.
2. When all the frequencies are integer divides of clk_out1:
  
  clk_out1
  
  1
  
  clk_out2
  
  2
  
  clk_out3
  
  3
  
  clk_out4
  
  4
  
  clk_out5
  
  5
  
  clk_out6
  
  6
  
  clk_out7
  
  7
  - Two MBUFGCEs (MBUFGCE1: clkout1, clkout2, clkout4, clkout7, and MBUFGCE2: clkout3, clkout6) and remaining clock (clkout6) with separate BUFG.
  - clk1_clr_n is available as clk_out1 is the input to MBUFGCE1, and clk3_clr_n also available as clk_out3 is the input to MBUFGCE2.
3. When some of the frequencies are the same as clk_out1 and some are integer divides of clk_out1:
  
  clk_out1
  
  1
  
  clk_out2
  
  1
  
  clk_out3
  
  1
  
  clk_out4
  
  1
  
  clk_out5
  
  2
  
  clk_out6
  
  3
  
  clk_out7
  
  4
  - Three clocks (clk_out1, clk_out5, clk_out7) can be derived from one MBUFGCE and remaining clocks (clkout2, clkout3, clkout4, clkout6) are derived from separate BUFG.
  - clk1_clr_n is available as clk_out1 is the input to MBUFGCE.
4. When only four clock outs are present and all are integer divides of clk_out:
  
  clk_out1
  
  1
  
  clk_out2
  
  2
  
  clk_out3
  
  4
  
  clk_out4
  
  8
  - MMCM primitive cannot be inferred in this case, and the IP infers MBUFGCE.
  - clk1_clr_n is available as clk_out1 is the input to MBUFGCE.
5. When the frequencies are divided by 1 or 2:
  
  clk_out1
  
  1
  
  clk_out2
  
  2
  
  clk_out3
  
  1
  
  clk_out4
  
  2
  
  clk_out5
  
  1
  
  clk_out6
  
  2
  
  clk_out7
  
  1
  - Three MBUFGCEs (MBUFGCE1: clk_out1, clk_out2; MBUFGCE2: clk_out3, clk_out4 and MBUFGCE3: clk_out5, clk_out2=6) and remaining clock (clkout7) is inferred through BUFG.
  - clk1_clr_n is available as clk_out1 is the input to MBUFGCE1, clk3_clr_n is available as clk_out3 is the input to MBUFGCE2 and clk5_clr_n is available as clk_out5 is the input to MBUFGCE3.
6. When all the frequencies are even integer divides of clk_out1:
  
  clk_out1
  
  1
  
  clk_out2
  
  2
  
  clk_out3
  
  2
  
  clk_out4
  
  4
  
  clk_out5
  
  4
  
  clk_out6
  
  6
  
  clk_out7
  
  8
  - Two MBUFGCE (MBUFGCE1: clk_out1, clk_out2, clk_out4, clk_out7 and MBUFGCE2: clk_out3, clk_out5) need to be used to infer six clock outs and the remaining clock (clkout6) needs to be inferred from BUFG.
  - clk1_clr_n is available as clk_out1 is the input to MBUFGCE1 and clk3_clr_n also available as clk_out3 is the input to MBUFGCE2.

Sample test case with clock grouping is selected

When all the frequencies are integer divides of clk_out1:

Table 1. Frequencies of Integer Divides of `clk_out1` and with Multiple Clock Grouping
clk_out	DIV	CLK GROUP
clk_out1	1	CLOCK A
clk_out2	2	CLOCK B
clk_out3	3	Auto
clk_out4	4	CLOCK A
clk_out5	5	Auto
clk_out6	6	Auto
clk_out7	8	CLOCK B

Three MBUFGCE (MBUFGCE1: clk_out1, clk_out4: MBUFGCE2: clk_out2, clk_out7 and MBUFGCE3: clk_out3, clk_out6) and remaining clock (clkout5) is inferred through BUFG.
clk1_clr_n is available as clk_out1 is the input to MBUFGCE1, clk2_clr_n is available as clk_out2 is the input to MBUFGCE2 and clk3_clr_n is available as clk_out3 is the input to MBUFGCE3.

The following are example combinations with Auto Buffer (drives selected as “Buffer with CE”) and Auto Clock Grouping:

When all the frequencies are independent of each other (no integer division between any of them), all clock outs are inferred with separate BUFGCE.
When all the frequencies of integer divides of clk_out1:

clk_out1

1

clk_out2

2

clk_out3

3

clk_out4

4

clk_out5

5

clk_out6

6

clk_out7

8
- Two MBUFGCEs (MBUFGCE1: clk_out1, clk_out2, clk_out4, clk_out7 and MBUFGCE2: clk_out3, clk_out6) and the remaining clock (clkout6) with separate BUFGCE.
- clk1_clr_n is available as clk_out1 is the input to MBUFGCE1, and clk3_clr_n also available as clk_out3 is the input to MBUFGCE2.
- clk1_ce is available as clk_out1 is the input to MBUFGCE1, clk3_ce also available as clk_out3 is the input to MBUFGCE2, and clk_out5_ce is also available as BUFGCE for clk_out5.
When some of the frequencies are same as clk_out1, and some are integer divides of clk_out1:

clk_out1

1

clk_out2

1

clk_out3

1

clk_out4

1

clk_out5

2

clk_out6

3

clk_out7

4
- Three clocks (clkout1, clkout5, clkout7) can be derived from one MBUFGCE, and the remaining clocks (clkout2, clkout3, clkout4, clkout6) are derived from separate BUFGCE.
- clk1_clr_n and clk1_ce are available as clk_out1 is the input to MBUFGCE
- clk_out2_ce, clk_out3_ce, clk_out4_ce, and clk_out6_ce are also available as four separate BUFGCE inferred.
When only four clock outs are used and all are integer divides of clk_out1:

clk_out1

1

clk_out2

2

clk_out3

4

clk_out4

8
- All four clocks can get from one MBUFGCE.
- clk1_clr_n and clk1_ce are available as clk_out1 is the input to MBUFGCE.
When the frequencies are divided by 1 or 2:

clk_out1

1

clk_out2

2

clk_out3

1

clk_out4

2

clk_out5

1

clk_out6

2

clk_out7

1
- Three MBUFGCEs (MBUFGCE1: clk_out1, clk_out2; MBUFGCE2: clk_out3, clk_out4 and MBUFGCE3: clk_out5, clk_out6) and the remaining clock (clkout7) is inferred through BUFGCE.
- clk1_clr_n, clk1_ce are available as clk_out1 is the input to MBUFGCE1, clk3_clr_n, clk3_ce are available as clk_out3 is the input to MBUFGCE2 and clk5_clr_n, clk5_ce are available as clk_out5 is the input to MBUFGCE3.
- clk_out7_ce is available as BUFGCE inferred for clk_out7
When all the frequencies are even integer divides of clk_out1:

clk_out1

1

clk_out2

2

clk_out3

2

clk_out4

4

clk_out5

4

clk_out6

6

clk_out7

8
- Two MBUFGCE (MBUFGCE1: clk_out1, clk_out2, clk_out4, clk_out7 and MBUFGCE2: clk_out3, clk_out5) need to be used to infer six clock outs and the remaining clock (clkout6) needs to be inferred from BUFGCE.
- clk1_clr_n, clk1_ce are available as clk_out1 is the input to MBUFGCE1 and clk3_clr_n, clk3_ce also are available as clk_out3 is the input to MBUFGCE2.
- clk_out6_ce is available as BUFGCE is inferred for clk_out6.

Sample test case with clock grouping is selected

When all the frequencies are integer divides of clk_out1:

Table 2. Frequencies of integer divides of `clk_out1`
clk_out	DIV	CLK GROUP
clk_out1	1	CLOCK A
clk_out2	2	CLOCK B
clk_out3	3	Auto
clk_out4	4	CLOCK A
clk_out5	5	Auto
clk_out6	6	Auto
clk_out7	8	CLOCK B

Three MBUFGCEs (MBUFGCE1: clk_out1, clk_out4; MBUFGCE2: clk_out2, clk_out7 and MBUFGCE3: clk_out3, clk_out6) and the remaining clock (clkout5) is inferred through BUFGCE.

Three MBUFGCE (MBUFGCE1: clk_out1, clk_out4; MBUFGCE2: clk_out2, clk_out7 and MBUFGCE3: clk_out3, clk_out6) and the remaining clock (clkout5) is inferred through BUFGCE.
clk1_clr_n, clk1_ce are available as clk_out1 is the input to MBUFGCE1, clk2_clr_n, clk2_ce are available as clk_out2 is the input to MBUFGCE2 and clk3_clr_n, clk3_ce are available as clk_out3 is the input to MBUFGCE3.
clk_out5_ce is available as BUFGCE inferred for clk_out5.

Note: In all the above cases, the *_clr_n pin connected to MBUFGCE is active-Low signal and tie to 1 for MBUFGCE to be active.

Auto Buffer Selection and Clock Grouping - Auto Buffer Selection and Clock Grouping - 1.0 English - PG321

Clocking Wizard for Versal Adaptive SoCs LogiCORE IP Product Guide (PG321)