Following table describes clock
configuration registers:
| Base Address + Offset (hex) | Register Name | Reset Value (hex) | Access Type | Description |
|---|---|---|---|---|
| C_BASEADDR + 0x00 | Software Reset Register (SRR) | N/A | W | To activate software reset, the value 0x0000_000A must be written to the register. Any other access, read or
write, has undefined results. |
| C_BASEADDR + 0x04 | Status Register (SR) |
0x00000000
|
R |
Bit[0] = Locked when 1 MMCM/PLL is locked and ready for reconfiguration. The status of this bit is 0 during reconfiguration. |
| C_BASEADDR + 0x08 | Clock Monitor Error Status Register |
0x00000000
|
R | This register gives the error status bits of the clock monitor feature. |
| C_BASEADDR + 0x0C | Interrupt Status |
0x00000000
|
R/W | Interrupt status for clock stop, clock overrun, and clock underrun. These bits are gated by interrupt enable bits. Interrupts corresponding to the enabled bits in interrupt enable register would be updated in the register. |
| C_BASEADDR + 0x10 | Interrupt Enable |
0x00000000
|
R/W | Interrupt enable for clock stop, clock overrun and clock underrun bits in the interrupt status register. |
| C_BASEADDR + 0x014 | Clock Configuration Register |
0000
|
R/W | Bit[0] = LOAD / SEN: Loads Clock Configuration Register values to
the internal register used for dynamic reconfiguration and initiates reconfiguration
state machine. This bit should be asserted when the required settings are already
written into Clock Configuration Registers. This bit retains to 0 when the dynamic
reconfiguration is done and the clock is locked. Bit[1] = SADDR: When written 0, default configuration done in the Clocking Wizard GUI is loaded for dynamic reconfiguration. When written 1, setting provided in the Clock Configuration Registers are used for dynamic reconfiguration. |
| C_BASEADDR + 0x330 | CLKFBOUT_1 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x334 | CLKFBOUT_2 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x338 | CLKOUT0_1 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x33C | CLKOUT0_2 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x340 | CLKOUT1_1 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x344 | CLKOUT1_2 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x348 | CLKOUT2_1 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x34C | CLKOUT2_2 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x350 | CLKOUT3_1 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x354 | CLKOUT3_2 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x378 | CP | TBD | R/W | Note 1 |
| C_BASEADDR + 0x37C | DESKEW_1 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x380 | DESKEW_2 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x384 | DIVCLK | TBD | R/W | Note 1 |
| C_BASEADDR + 0x390 | INTERPOL_1 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x394 | INTERPOL_2 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x398 | LF | TBD | R/W | Note 1 |
| C_BASEADDR + 0x39C | LOCK_1 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x3A0 | LOCK_2 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x3A8 | RES_1 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x3AC | RES_2 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x3C0 | UNLOCK_CNT | TBD | R/W | Note 1 |
| C_BASEADDR + 0x3CC | CLKOUT4_1 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x3D0 | CLKOUT4_2 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x3D4 | CLKOUT5_1 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x3D8 | CLKOUT5_2 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x3DC | CLKOUT6_1 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x3E0 | CLKOUT6_2 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x3E4 | INTERPOL_3 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x3E8 | INTERPOL_4 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x3F0 | CLKFBOUT_3 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x3F8 | SS | TBD | R/W | Note 1 |
| C_BASEADDR + 0x3FC | CLKFBOUT_4 | TBD | R/W | Note 1 |
| C_BASEADDR + 0x3FF to C_BASEADDR + 0xFFF | Undefined | Undefined | N/A | Do not read/write these registers. |
|
||||