The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 10/26/2022 Version 1.0 | |
| Output Clock Ports | Added additional buffer BUFG_GT. |
| 04/20/2022 Version 1.0 | |
| Digital Deskew for DPLL | Added new section |
| Status and Control Ports | Updated Clocking Wizard Status and Control Ports table note |
| Clock Monitor | Updated Clock Stop section |
| 06/30/2021 Version 1.0 | |
| Applications | Updated with additional information |
| Clock Monitor | Updated with additional information |
| Summary | Updated with additional information |
| Figure 1 | Updated image |
| Deskew Feature Support for Versal | Added new feature |
| Auto Buffer Selection and Clock Grouping | Updated the content |
| Input Clock Ports | Added new ports to the list |
| Master Answer Record for the Core | Updated new Answer Record |
| 02/02/2021 Version 1.0 | |
| Feature Summary | Added Safe Clock Startup. |
| Figure 1 | Updated figure. |
| Table 1 | Updated table. |
| Clocking Features | Added new features. |
| Clock Monitor | Added new features. |
| Table 1 | Updated table. |
| Figure 1 | Updated figure. |
| Figure 1 | Updated figure. |
| Summary | Added new features. |
| Auto Buffer Selection and Clock Grouping | Added information about "Buffer with CE." |
| Safe Clock Startup | Added new section. |
| User Parameters | Added new features. |
| Simulation | Added new features. |
| Unsupported Features in Example Design | Added new unsupported features. |
| 07/14/2020 Version 1.0 | |
| Initial release. | N/A |