Port Name | I/O | Description |
---|---|---|
clk_in1
|
Input |
Clock in 1: Single-ended primary input clock port. Available when single-ended primary clock source is selected. |
clk_in1_p
|
Input | Clock in 1 Positive and Negative: Differential primary input clock port pair. Available when a differential primary clock source is selected. |
clk_in1_n
|
||
clk_in2
1
|
Input |
Clock in 2: Single-ended secondary input clock port. Available when a single-ended secondary clock source is selected. |
clk_in2_p
1
|
Input | Clock in 2 Positive and Negative: Differential secondary input clock port pair. Available when a differential secondary clock source is selected. |
clk_in2_n
1
|
||
clk_in_sel
1
|
Input |
Clock in Select: When set to 1,
the secondary input clock is enabled and when set to 0, the primary input clock is
enabled. Note: This port is available only when the secondary clock is enabled
using GUI.
|
clkfb_in
|
Input | Clock Feedback in: Single-ended feedback in port of the clocking primitive. Available when user-controlled on-chip, user controller-off chip, or automatic control off-chip feedback option is selected. |
clkfb_in_p
|
Input | Clock Feedback in: Positive and Negative: Differential feedback in port of the clocking primitive. Available when the automatic control off-chip feedback and differential feedback option is selected. |
clkfb_in_n
|
||
clkin1_deskew
|
Input | Clock in for DESKEW PD1 Network: Single ended clock in deskew port is available when DESKEW1_IN is selected as "clk_ext" if any of the clock out (clk_out1 to clk_out7) PI Control is selected as DESKEW_PD1 |
clkin2_deskew
|
Input | Clock in for DESKEW PD2 Network: Single ended clock in deskew port is available when DESKEW2_IN is selected as "clk_ext" if any of the clock out (clk_out1 to clk_out7) PI Control is selected as DESKEW_PD2 |
clkfb1_deskew
|
Input |
Clock fb for DESKEW PD1 Network:
Single ended clock fb deskew port is available when any of the clock out (clk_out2
to clk_out7) PI Control is selected as DESKEW_PD1
and drives is selected as No_buffer for that
particular clock and Deskew1 FB value in Deskew Network pane selected as per the
clk_out (2 for clk_out2, 3 for clk_out3 etc) |
clkfb2_deskew
|
Input |
Clock fb for DESKEW PD2 Network:
Single ended clock fb deskew port is available when any of the clock out (clk out2
to clk_out7) PI Control is selected as DESKEW_PD2
and drives is selected as No_buffer for that
particular clock and Deskew2 FB value in Deskew Network pane selected as per the
clk_out (2 for clk_out2, 3 for clk_out3 etc) |
ref_clk
|
Input | Refernce clock: This is the input reference clock used to monitor the user clocks. It is considered to be stable and error free. |
user_clk0
|
Input | User Clock0: This port is disabled when the ENABLE_DPLL/PLL/MMCM0 checkbox is enabled in the Vivado IDE. This option is enabled when you select the Clock Monitor. |
user_clk1
|
Input | User Clock1: This port is disabled when the ENABLE_DPLL/PLL/MMCM1 checkbox is enabled in the Vivado IDE. This option is enabled when you select Clock Monitor. |
user_clk2
|
Input | User Clock2: User input clock 2 to monitor. This option is enabled when you select Clock Monitor. |
user_clk3
|
Input | User Clock3: User input clock 3 to monitor. This option is enabled when you select Clock Monitor. |
|