Dynamic Reconfiguration through AXI4-Lite - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)
Document ID
PG321
Release Date
2022-10-26
Version
1.0 English

The Clocking Wizard core provides an AXI4-Lite interface for the dynamic reconfiguration of the clocking primitive MMCM/XPLL/DPLL. This interface is enabled when Dynamic Reconfiguration is enabled. Mixed language RTL is delivered by the core when AXI4-Lite interface is used.

Important: This feature is not supported when Spread Spectrum is enabled and also when Digital Deskew for DPLL is enabled.

Register Space provides details of the signals of AXI4-Lite and the tables in the Register Space section provide details of the clock configuration registers.

The Clocking Wizard core uses a configuration state machine listed in and extends from two fixed state configuration to program any valid range of multiply, divide, phase, and duty cycle. In this state machine, State 1 corresponds to default state configured through Clocking Wizard interface. State 2 corresponds to user-configuration loaded into the clock configuration register detailed in the tables in Register Space. State 2 values are also initialized with the State 1 values so that a valid configuration is stored by default. All the dynamic reconfiguration registers are to be updated whenever you want to reprogram the clock.

Perform the following steps for dynamic reconfiguration:

  1. Generate the Clocking Wizard IP enabling dynamic reconfiguration.
  2. Open another Clocking Wizard with the same input clock and the features as intended.
  3. Now, change the output clock features in the output clock tab of the Vivado® IDE as required for dynamic reconfiguration.
  4. Generate the IP.
  5. A file with name <component_name>_drp_address_map gets generated in the IP sources area. This file has the address and the data which needs to be written into AXI interface for reconfiguring.
  6. After writing all the registers in the file, now write address 0x014 with 0x03 as mentioned in the register map to initiate the reconfiguration.

An example of this feature has been described in the following section.

Figure 1. Dynamic Reconfiguration using AXI4-Lite Interface Page-1 Rectangle.427 AXI Lite Interface AXI LiteInterface Rectangle.2 Software Reset Register Software ResetRegister Rectangle.140 Data & Control Registers (R/W) Data & ControlRegisters (R/W) Rectangle.141 Status Register Status Register Rectangle.142 Mmcm/pll_drp Mmcm/pll_drp Rectangle.143 MMCM/PLL MMCM/PLL Rectangle.144 Rectangle.145 1-D double.435 Standard Arrow.436 Standard Arrow.437 Standard Arrow.149 Standard Arrow.150 Sheet.153 DCLK DCLK Sheet.156 RST RST Sheet.151 DI[15:0] DI[15:0] Sheet.154 DADDR[6:0] DADDR[6:0] Sheet.157 DEN DEN Sheet.158 DWE DWE Sheet.161 LOCKED LOCKED Sheet.159 DRDY DRDY Sheet.162 Sheet.163 32 32 Sheet.164 Standard Arrow.47 Mux_2:1.445 Sheet.166 Sheet.167 32 32 Sheet.168 Standard Arrow.169 Sheet.170 Sheet.172 32 32 Sheet.173 Dynamic connector Sheet.175 Sheet.176 32 32 Sheet.177 Standard Arrow.178 Standard Arrow.179 Standard Arrow.180 Sheet.182 32 32 Sheet.183 Sheet.181 Sheet.184 Standard Arrow.185 Sheet.186 DO[15:0] DO[15:0] Dynamic connector.187 Sheet.189 7 7 Sheet.190 Sheet.188 16 16 Sheet.191 Sheet.192 16 16 Sheet.193 Graphic ID: SW & IP X13970 X13970

Example for Dynamic Reconfiguration through AXI4-Lite

The input and output clock frequencies are 100 MHz in the Clocking Wizard by default.

  1. The output clock frequency needs to be reconfigured to 50 MHz with a phase shift of 90 degrees.
  2. The file gets generated in the sources area as shown below.

  3. The file specifies all the AXI Registers with the address and the data which needs to be written into it. Configure all the AXI Registers with respect to the table.
  4. Configure the address: C_BASEADDR + 0x014 with 0x00000003 to set the LOAD and SEN bits.
  5. Wait for the locked signal. The new frequency can be checked at clkout1 output port.
Note:
  1. DRP interface is not supported for Versal® devices, APB3 interface is used internally. For details on DRP/APB3 ports, see Versal ACAP Clocking Resources Architecture Manual (AM003).
  2. While reconfiguring, even reconfiguring for one clock output, all other active clock outputs will be reset.